User’s Manual U16896EJ2V0UD
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CHAPTER 3 CPU FUNCTIONS
The CPU of the V850ES/KE1+ is based on the RISC architecture and executes most instructions in one clock
cycle by using 5-stage pipeline control.
3.1 Features
{
Number of instructions:
83
{
Minimum instruction execution time: 50.0 ns (@ 20 MHz operation: 4.5 to 5.5 V)
100 ns (@ 10 MHz operation: 2.7 to 5.5 V)
{
Memory space
Program (physical address) space: 64 MB linear
Data (logical address) space:
4 GB linear
{
General-purpose registers: 32 bits
×
32
{
Internal 32-bit architecture
{
5-stage pipeline control
{
Multiply/divide instructions
{
Saturated operation instructions
{
32-bit shift instruction: 1 clock
{
Load/store instruction with long/short format
{
Four types of bit manipulation instructions
•
SET1
•
CLR1
•
NOT1
•
TST1
<R>
