CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U16896EJ2V0UD
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7.4.5 Free-running timer operation
When the TMC01.TMC013 and TMC01.TMC012 bits are set to 01 (free-running timer mode), 16-bit timer/event
counter 01 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the
overflow flag (TMC01.OVF01 bit) is set to 1 at the next clock, and the TM01 register is cleared (to 0000H) and
continues counting. Clear the OVF01 bit to 0 by executing the CLR instruction via software.
The following three types of free-running timer operations are available.
•
Both the CR010 and CR011 registers are used as compare registers.
•
Either the CR010 register or CR011 register is used as a compare register and the other is used as a capture
register.
•
Both the CR010 and CR011 registers are used as capture registers.
Remarks 1.
For the alternate-function pin (TO01) settings, refer to
Table 4-12 Settings When Port Pins Are
Used for Alternate Functions
.
2.
For enabling the INTTM010 and INTTM011 interrupts, refer to
CHAPTER 17 INTERRUPT/EXCEPTION
PROCESSING FUNCTION
.
(1) Free-running timer mode operation
(CR010 register: compare register, CR011 register: compare register)
Figure 7-23. Block Diagram of Free-Running Timer Mode
(CR010 Register: Compare Register, CR011 Register: Compare Register)
16-bit counter
(TM01)
Output
controller
Compare register
(CR011)
Match signal
TO01 pin
Match signal
Interrupt signal
(INTTM010)
Interrupt signal
(INTTM011)
Compare register
(CR010)
Operable bits
TMC013, TMC012
Count clock
