CHAPTER 21 CLOCK MONITOR
User’s Manual U16896EJ2V0UD
608
21.4 Internal Oscillation Clock Operation Mode
21.4.1 Setting and operation status
If watchdog timer 2 overflows during the oscillation stabilization time securing period after a reset is released or
after the STOP mode is released (overflow of the counter by setting the OSTS register), the internal oscillation clock
operation mode is set.
For details, refer to
Figure 19-1 Status Transition
.
A stop (error) of the main clock oscillation (f
X
) is detected when as shown below.
•
During normal operation: When the main clock is monitored by the internal oscillation clock (clock monitor)
•
During oscillation stabilization time securing period: When WDT2 overflow occurs
Table 21-3 shows the operation status in the internal oscillation clock operation mode.
Table 21-2. Overflow Time of OSTS Register and Watchdog Timer 2
Overflow
Time
Option
Note
: 2
13
/f
X
0.819 ms @ 10 MHz, 1.638 ms @ 5 MHz
After reset release
Option
Note
: 2
15
/f
X
3.277 ms @ 10 MHz, 6.554 ms @ 5 MHz
Counter overflow time by
OSTS register setting
After STOP mode release by interrupt
(OSTS = 2
13
/f
X
to 2
21
/f
X
)
0.819 ms @ 10 MHz, 1.638 ms @ 5 MHz (MIN.)
209.7 ms @ 10 MHz, 419.4 ms @ 5 MHz (MAX.)
After reset release (2
19
/f
R
)
1,092 ms to 4,369 ms
Watchdog timer 2 overflow
time
After STOP mode release by interrupt
(WDTM2 = 2
12
/f
R
to 2
19
/f
R
)
8.5 ms to 34.1 ms (MIN.)
1,092 ms to 4,369 ms (MAX.)
Note
The oscillation stabilization time can be changed by setting the mask option/option byte. For details, refer to
CHAPTER 25 MASK OPTION/OPTION BYTE
.
Cautions 1. Set so as to make the watchdog timer 2 overflow time longer than the oscillation stabilization
time (OSTS register setting). If the watchdog timer 2 overflow time is shorter than the
oscillation stabilization time (OSTS register setting), the oscillation is incorrectly judged as
stopped, regardless of whether the main clock oscillation is correctly operating when the
STOP mode is released by an interrupt. The internal oscillation clock operation mode will
then be unintentionally set.
2. When the internal oscillation clock operation mode is set, do not rewrite the WDTM2 and
WDTE registers in 1,024 internal oscillation clocks (f
R
) after the CPU operation is started.
21.4.2 Releasing internal oscillation clock operation mode
The internal oscillation clock operation mode is released by reset (RESET input, WDT reset, etc.).
While securing the oscillation stabilization time after reset is released, if the OSTS register overflows before
watchdog timer 2 overflows, the main clock oscillation (f
X
) is judged as stabilized and the normal operation mode is
set.
For details, refer to
Figure 19-1 Status Transition
.
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