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Index for Volumes 1, 2, 3 and 4

Index:1

INDEX FOR VOLUMES 1, 2, 3 AND 4

AAA Instruction 4:21
AAD Instruction 4:22
AAM Instruction 4:23
AAS Instruction 4:24
Aborts 2:95, 2:538
ACPI 2:631

Acquire Semantics 2:507
ADC Instruction 4:25, 4:26
ADD Instruction 4:27, 4:28
add Instruction 3:14
addp4 Instruction 3:15
ADDPS Instruction 4:486
Address Space Model 2:561
ADDSS Instruction 4:487
Advanced Load 1:153, 1:154
Advanced Load Address Table (ALAT) 1:64
Advanced Load Check 1:154
ALAT (Advanced Load Address Table) 1:64

Coherency 2:554
Data Speculation 1:17

alloc Instruction 3:16
AND Instruction 4:29, 4:30
and Instruction 3:18
andcm Instruction 3:19
ANDNPS Instruction 4:488
ANDPS Instruction 4:489
Application Architecture Guide 1:1
Application Memory Addressing Model 1:36
Application Register (AR) 1:23, 1:28, 1:140
AR (Application Register) 1:28, 1:140
Arithmetic Instructions 1:51
ARPL Instruction 4:31, 4:32

Backing Store 2:133
Banked General Registers 2:42
Bit Field and Shift Instructions 1:52
Bit Strings 1:84
Boot Sequence 2:13
BOUND Instruction 4:33
BR (Branch Register) 1:26, 1:140
br Instruction 3:20

br.ia 1:112, 2:596

Branch Hints 1:78, 1:176
Branch Instructions 1:74, 1:145
Branch Register (BR) 1:19, 1:26, 1:140
break Instruction 2:556, 3:29
Break Instruction Fault 2:151
brl Instruction 3:30
brp Instruction 3:32
BSF Instruction 4:35
BSP (RSE Backing Store Pointer Register) 1:29
BSPSTORE (RSE Backing Store Pointer for Memory

Stores Register) 1:30

BSR Instruction 4:37
bsw Instruction 3:34
BSWAP Instruction 4:39
BT Instruction 4:40
BTC Instruction 4:42
BTR Instruction 4:44
BTS Instruction 4:46
Bundle Format 1:38
Bundles 1:38, 1:141
Byte Ordering 1:36

CALL Instruction 4:48
CBW Instruction 4:57
CCV (Compare and Exchange Value Register) 1:30
CDQ Instruction 4:85
CFM (Current Frame Marker) 1:27
Character Strings 1:83
Check Code 1:161
Check Load 1:154
chk Instruction 3:35
CLC Instruction 4:59
CLD Instruction 4:60
CLI Instruction 4:61
clrrrb Instruction 3:37
CLTS Instruction 4:63
clz Instruction 3:38
CMC (Corrected Machine Check) 2:350
CMC Instruction 4:64
CMCV (Corrected Machine Check Vector) 2:126
CMP Instruction 4:69
cmp Instruction 3:39
cmp4 Instruction 3:43
CMPPS Instruction 4:490
CMPS Instruction 4:71
CMPSB Instruction 4:71
CMPSD Instruction 4:71
CMPSS Instruction 4:493
CMPSW Instruction 4:71
CMPXCHG Instruction 4:74
cmpxchg Instruction 2:508, 3:46
CMPXCHG8B Instruction 4:76
Coalescing Attribute 2:78
COMISS Instruction 4:496
Compare and Exchange Value Register (CCV) 1:30
Compare and Store Data Register (CSD) 1:30
Compare Types 1:55
Context Management 2:549
Context Switching 2:557

Operating System Kernel 2:558
User-Level 2:557

Control Dependencies 1:148
Control Registers 2:29
Control Speculation 1:16, 1:60, 1:142, 1:151,

Summary of Contents for Itanium 9150M

Page 1: ......

Page 2: ...Intel Itanium Architecture Software Developer s Manual Volume 3 Intel Itanium Instruction Set Reference Revision 2 3 May 2010 Document Number 323207...

Page 3: ...anges to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel...

Page 4: ...n Encodings 3 300 4 2 1 Integer ALU 3 300 4 2 2 Integer Compare 3 302 4 2 3 Multimedia 3 306 4 3 I Unit Instruction Encodings 3 310 4 3 1 Multimedia and Variable Shifts 3 310 4 3 2 Integer Shifts 3 31...

Page 5: ...Listing of Rules Referenced in Dependency Tables 3 387 5 4 Support Tables 3 389 Index 3 397 Figures 2 1 Add Pointer 3 15 2 2 Stack Frame 3 16 2 3 Operation of br ctop and br cexit 3 23 2 4 Operation...

Page 6: ...ght Pair 3 248 2 45 Unpack Operation 3 271 4 1 Bundle Format 3 293 Tables 2 1 Instruction Page Description 3 11 2 2 Instruction Page Font Conventions 3 11 2 3 Register File Notation 3 12 2 4 C Syntax...

Page 7: ...Saturation Limits 3 227 2 50 Store Types 3 251 2 51 Store Hints 3 252 2 52 xsz Mnemonic Values 3 258 2 53 Test Bit Relations for Normal and unc tbits 3 261 2 54 Test Bit Relations for Parallel tbits...

Page 8: ...Pair Set FR Opcode Extensions 3 327 4 38 Floating point Load Pair Imm Opcode Extensions 3 328 4 39 Load Hint Completer 3 328 4 40 Store Hint Completer 3 328 4 41 Line Prefetch Hint Completer 3 337 4 4...

Page 9: ...it Opcode Extensions 3 366 4 70 Misc X Unit 6 bit Opcode Extensions 3 366 4 71 Move Long 1 bit Opcode Extensions 3 367 4 72 Long Branch Types 3 367 4 73 Misc X Unit 1 bit Opcode Extensions 3 368 4 74...

Page 10: ...e Itanium application architecture including application level resources programming environment and the IA 32 application interface This volume also describes optimization techniques used to generate...

Page 11: ...oftware 1 2 1 Part 1 System Architecture Guide Chapter 1 About this Manual provides an overview of all volumes in the Intel Itanium Architecture Software Developer s Manual Chapter 2 Intel Itanium Sys...

Page 12: ...ng systems need to preserve Itanium register contents and state This chapter also describes system architecture mechanisms that allow an operating system to reduce the number of registers that need to...

Page 13: ...Instruction Reference provides a detailed description of all Itanium instructions organized in alphabetical order by assembly language mnemonic Chapter 3 Pseudo Code Functions provides a table of pse...

Page 14: ...nvironment The operating system environment that supports the execution of both IA 32 and Itanium architecture based code Itanium Architecture based Firmware The Processor Abstraction Layer PAL and Sy...

Page 15: ...rmware 1 7 Revision History Date of Revision Revision Number Description March 2010 2 3 Added information about illegal virtualization optimization combinations and IIPA requirements Added Resource Ut...

Page 16: ...ocedures Allows IPI redirection feature to be optional Undefined behavior for 1 byte accesses to the non architected regions in the IPI block Modified insertion behavior for TR overlaps See Vol 2 Part...

Page 17: ...2 2 and 3 Part I Volume 3 Added Performance Counter Standardization Sections 7 2 3 and 11 6 Part I Volume 2 Added Freeze Bit Functionality in Context Switching and Interrupt Generation Clarification...

Page 18: ...changes extend calls to allow implementation specific feature control Section 11 8 3 Split PAL_A architecture changes Section 11 1 6 Simple barrier synchronization clarification Section 13 4 2 Limite...

Page 19: ...lify the call to provide more information regarding machine check Chapter 11 PAL_ENTER_IA_32_Env call changes entry parameter represents the entry order SAL needs to initialize all the IA 32 registers...

Page 20: ...ddr field specifies a register address as an assembly language field name or a register mnemonic For the general floating point and predicate register files which undergo register renaming addr is the...

Page 21: ...tion registers CPUID cpuid Y Data breakpoint registers DBR dbr Y Instruction breakpoint registers IBR ibr Y Data TLB translation cache DTC N A Data TLB translation registers DTR dtr Y Floating point r...

Page 22: ...ium instructions Table 2 5 Pervasive Conditions Not Included in Instruction Description Code Condition Action Read of a register outside the current frame An undefined value is returned no fault Acces...

Page 23: ...ended imm22 encoding field In the imm22_form GR r3 can specify only GRs 0 1 2 and 3 The plus1_form is available only in the register_form although the equivalent effect in the immediate forms can be a...

Page 24: ...t is placed in GR r1 In the register_form the first operand is GR r2 in the imm14_form the first operand is taken from the sign extended imm14 encoding field Operation if PR qp check_target_register r...

Page 25: ...ame and be a multiple of 8 in number If this instruction attempts to change the size of CFM sor and the register rename base registers CFM rrb gr CFM rrb fr CFM rrb pr are not all zero then the instru...

Page 26: ...te 0 tmp_sof CFM sof rse_new_frame CFM sof tmp_sof Make room for new registers Mandatory RSE stores can raise faults listed below CFM sof tmp_sof CFM sol tmp_sol CFM sor tmp_sor GR r1 AR PFS GR r1 nat...

Page 27: ...cally ANDed and the result placed in GR r1 In the register_form the first operand is GR r2 in the imm8_form the first operand is taken from the imm8 encoding field Operation if PR qp check_target_regi...

Page 28: ...1 s complement of the second source operand and the result placed in GR r1 In the register_form the first operand is GR r2 in the imm8_form the first operand is taken from the imm8 encoding field Oper...

Page 29: ...on as a signed immediate displacement imm21 between the target bundle and the bundle containing this instruction imm21 target25 IP 4 For indirect branches the target address is taken from BR b2 There...

Page 30: ...to the current code segment i e EIP 31 0 BR b2 31 0 CSD base The IA 32 instruction set can be entered at any privilege level provided PSR di is 0 If PSR dfh is 1 a Disabled FP Register fault is raised...

Page 31: ...gister is not equal to zero it is decremented and the branch is taken In addition to these simple branch types there are four types which are used for accelerating modulo scheduled loops see also Sect...

Page 32: ...on of whether to branch or not For br wtop the branch is taken if either the qualifying predicate is one or EC is greater than one For br wexit the opposite is true It is not taken if either the quali...

Page 33: ...ying predicate and PR 63 cannot be the qualifying predicate for any branch preceding a br wtop or br wexit in the same instruction group For dependency purposes the loop type branches effectively alwa...

Page 34: ...frame AR PFS pec AR EC AR PFS ppl PSR cpl alat_frame_update CFM sol 0 rse_preserve_frame CFM sol CFM sof CFM sol new frame size is size of outs CFM sol 0 CFM sor 0 CFM rrb gr 0 CFM rrb fr 0 CFM rrb pr...

Page 35: ...se_enable_current_frame_load AR EC AR PFS pec if PSR cpl u AR PFS ppl and restores privilege PSR cpl AR PFS ppl lower_priv_transition 1 break case ia switch to IA mode tmp_taken 1 if PSR ic 0 PSR dt 0...

Page 36: ...s else if AR EC 0 AR LC AR LC AR EC PR 63 0 rotate_regs else AR LC AR LC AR EC AR EC PR 63 0 CFM rrb gr CFM rrb gr CFM rrb fr CFM rrb fr CFM rrb pr CFM rrb pr break case wtop case wexit SW pipelined w...

Page 37: ...ted_instruction_address_trap lower_priv_transition tmp_IP if lower_priv_transition PSR lp lower_privilege_transfer_trap if PSR tb taken_branch_trap Interruptions Illegal Operation fault Lower Privileg...

Page 38: ...trol register IIM For the x_unit_form the lower 21 bits of the value specified by imm62 is zero extended and placed in the Interruption Immediate control register IIM The L slot of the bundle contains...

Page 39: ...taken and several other actions occur The current values of the Current Frame Marker CFM the EC application register and the current privilege level are saved in the Previous Function State applicatio...

Page 40: ...tmp_taken PR qp break case call call saves a return link tmp_taken PR qp if tmp_taken BR b1 IP 16 AR PFS pfm CFM and saves the stack frame AR PFS pec AR EC AR PFS ppl PSR cpl alat_frame_update CFM sol...

Page 41: ...branch In the indirect_form the target of the presaged branch is given by BR b2 The return_form is used to indicate that the presaged branch will be a return Other hints can be given about the presage...

Page 42: ...brp Operation tmp_tag IP sign_ext timm9 4 13 if ip_relative_form tmp_target IP sign_ext imm21 4 25 tmp_wh ipwh else indirect_form tmp_target BR b2 tmp_wh indwh branch_predict tmp_wh ih return_form tm...

Page 43: ...an instruction group otherwise operation is undefined Instructions in the same instruction group that access GR16 to GR31 reference the previous register bank Subsequent instruction groups reference t...

Page 44: ...is encoded in the instruction as a signed immediate displacement imm21 between the target bundle and the bundle containing this instruction imm21 target25 IP 4 The branching behavior of this instruct...

Page 45: ...always_fail alat_index 0 alat_index 1 fail always_fail alat_cmp reg_type alat_index if fail if check_branch_implemented check_type taken_branch 1 IP IP sign_ext imm21 4 25 if impl_uia_fault_supported...

Page 46: ...b pr are cleared In the pred_form the single register rename base register for the predicates CFM rrb pr is cleared This instruction must be the last instruction in an instruction group otherwise oper...

Page 47: ...ndicates the presence of the feature on the processor model See Section 3 1 11 Processor Identification Registers on page 1 34 for details This capability may also be determined using the test feature...

Page 48: ...Table 2 15 A blank entry indicates the predicate target is left unchanged In the register_form the first operand is GR r2 in the imm8_form the first operand is taken from the sign extended imm8 encodi...

Page 49: ...0 Comparisons where the second operand is GR 0 are pseudo ops for which the assembler switches the register specifiers and uses the opposite relation Table 2 16 64 bit Comparison Relations for Normal...

Page 50: ...p_rel greater_signed tmp_src GR r3 else if crel ge tmp_rel greater_equal_signed tmp_src GR r3 else if crel ltu tmp_rel lesser tmp_src GR r3 else if crel leu tmp_rel lesser_equal tmp_src GR r3 else if...

Page 51: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault...

Page 52: ...the sign extended imm8 encoding field and in the parallel_inequality_form the first operand must be GR 0 The parallel_inequality_form is only used when the compare type is one of the parallel types a...

Page 53: ...c 32 sign_ext GR r3 32 else if crel gt tmp_rel greater_signed sign_ext tmp_src 32 sign_ext GR r3 32 else if crel ge tmp_rel greater_equal_signed sign_ext tmp_src 32 sign_ext GR r3 32 else if crel ltu...

Page 54: ...mp4 PR p2 0 break case unc unc type compare default normal compare if tmp_nat PR p1 0 PR p2 0 else PR p1 tmp_rel PR p2 tmp_rel break else if ctype unc if p1 p2 illegal_operation_fault PR p1 0 PR p2 0...

Page 55: ...y the value in GR r3 is not naturally aligned to the size of the value being accessed in memory an Unaligned Data Reference fault is taken independent of the state of the User Mask alignment checking...

Page 56: ...rts_semaphores mattr unsupported_data_reference_fault SEMAPHORE GR r3 if sixteen_byte_form if sem acq val mem_xchg16_cond AR CCV GR r2 AR CSD paddr UM be mattr ACQUIRE ldhint else rel val mem_xchg16_c...

Page 57: ...then the old value of the Current Frame Marker CFM is copied to the Interruption Function State register IFS and IFS v is set to one A cover instruction must be the last instruction in an instruction...

Page 58: ...000000000 0 GR r1 2 else if GR r3 0x000000ff00000000 0 GR r1 3 else if GR r3 0x00000000ff000000 0 GR r1 4 else if GR r3 0x0000000000ff0000 0 GR r1 5 else if GR r3 0x000000000000ff00 0 GR r1 6 else if...

Page 59: ...3 50 Volume 3 Instruction Reference czx else if GR r3 0x0000ffff00000000 0 GR r1 2 else if GR r3 0xffff000000000000 0 GR r1 3 else GR r1 4 GR r1 nat GR r3 nat Interruptions Illegal Operation fault...

Page 60: ...n the imm_form The pos6 immediate has a range of 0 to 63 In the zero_form a right justified bit field taken from either the value in GR r2 in the register_form or the sign extended value in imm8 in th...

Page 61: ...mm8 8 tmp_nat merge_form GR r3 nat 0 tmp_len len6 else register_form tmp_src GR r2 tmp_nat merge_form GR r3 nat 0 GR r2 nat tmp_len merge_form len4 len6 if pos6 tmp_len u 64 tmp_len 64 pos6 if merge_f...

Page 62: ...the translation for the page containing the epc instruction This instruction can promote but cannot demote and the new privilege comes from the TLB entry If instruction address translation is disable...

Page 63: ...t significant bit of the extracted field If the specified field extends beyond the most significant bit of GR r3 the sign is taken from the most significant bit of GR r3 The immediate value len6 can b...

Page 64: ...ue Format qp fabs f1 f3 pseudo op of qp fmerge s f1 f0 f3 Description The absolute value of the value in FR f3 is computed and placed in FR f1 If FR f3 is a NaTVal FR f1 is set to NaTVal instead of th...

Page 65: ...al FR f1 is set to NaTVal instead of the computed result The mnemonic values for the opcode s pc are given in Table 2 22 The mnemonic values for sf are given in Table 2 23 For the encodings and interp...

Page 66: ...s for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disabled f1 f2 f3 0 disabled_fp_register_fault tmp_isrcode 0 if fp_is_natval FR f2 fp...

Page 67: ...es for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disabled f1 f2 f3 0 disabled_fp_register_fault tmp_isrcode 0 if fp_is_natval FR f2 f...

Page 68: ...gn field of FR f1 is set to positive 0 If either FR f2 or FR f3 is a NaTVal FR f1 is set to NaTVal instead of the computed result Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_d...

Page 69: ...for 2 063 0x1003E and the sign field of FR f1 is set to positive 0 If either FR f2 or FR f2 is a NaTVal FR f1 is set to NaTVal instead of the computed result Operation if PR qp fp_check_target_registe...

Page 70: ...s aligned on a 32 byte boundary An implementation may flush a larger region When executed at privilege level 0 fc and fc i perform no access rights or protection key checks At other privilege levels f...

Page 71: ...nterruptions Register NaT Consumption fault Data TLB fault Unimplemented Data Address fault Data Page Not Present fault Data Nested TLB fault Data NaT Page Consumption fault Alternate Data TLB fault D...

Page 72: ...on fault is taken and the value specified by imm21 is zero extended and placed in the Interruption Immediate control register IIM The fault handler emulates the branch by sign extending the IIM value...

Page 73: ...or the number is a quiet NaN and fclass9 7 is 1 or the number is a signaling NaN and fclass9 6 is 1 or the sign of the number agrees with the sign specified by one of the two low order bits of fclass...

Page 74: ...s_zero FR f2 fclass9 3 fp_is_unorm FR f2 fclass9 4 fp_is_normal FR f2 fclass9 5 fp_is_inf FR f2 fclass9 6 fp_is_snan FR f2 fclass9 7 fp_is_qnan FR f2 fclass9 8 fp_is_natval FR f2 tmp_nat fp_is_natval...

Page 75: ...ing point Clear Flags Format qp fclrf sf F13 Description The status field s 6 bit flags field is reset to zero The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_set...

Page 76: ...do ops For these the assembler simply switches the source operand specifiers and or switches the predicate target specifiers and uses an implemented relation Table 2 26 Floating point Comparison Types...

Page 77: ...an tmp_fr2 tmp_fr3 else if frel le tmp_rel fp_lesser_or_equal tmp_fr2 tmp_fr3 else if frel gt tmp_rel fp_less_than tmp_fr3 tmp_fr2 else if frel ge tmp_rel fp_lesser_or_equal tmp_fr3 tmp_fr2 else if fr...

Page 78: ...on Reference 3 69 fcmp FP Exceptions Invalid Operation V Denormal Unnormal Operand D Software Assist SWA fault Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating po...

Page 79: ...tion Floating point Exception fault is disabled If FR f2 is a NaTVal FR f1 is set to NaTVal instead of the computed result The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if...

Page 80: ...fx FP Exceptions Invalid Operation V Inexact I Denormal Unnormal Operand D Software Assist SWA fault Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Regis...

Page 81: ...s unaffected by the rounding mode Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disabled f1 f2 0 0 disabled_fp_register_fault tmp_isrcode 0 if fp_is_natval FR f2 FR f1 NATVAL el...

Page 82: ...e Multiplying FR f3 with FR 1 a 1 0 normalizes the canonical representation of an integer in the floating point register file producing a normal floating point value If FR f3 is a NaTVal FR f1 is set...

Page 83: ...endent of the state of the User Mask alignment checking bit UM ac PSR ac in the Processor Status Register Both read and write access privileges for the referenced page are required The write access pr...

Page 84: ...else rel val mem_xchg_add inc3 paddr size UM be mattr RELEASE ldhint alat_inval_multiple_entries paddr size GR r1 zero_ext val size 8 GR r1 nat 0 Interruptions Illegal Operation fault Data Key Miss f...

Page 85: ...instruction completes execution BSPSTORE is equal to BSP This instruction must be the first instruction in an instruction group and must either be in instruction slot 0 or in instruction slot 1 of a...

Page 86: ...2 23 on page 3 56 For the encodings and interpretation of the status field s pc wre and rc refer to Table 5 5 and Table 5 6 on page 1 90 Operation if PR qp fp_check_target_register f1 if tmp_isrcode...

Page 87: ...3 78 Volume 3 Instruction Reference fma Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault Floating point Exception trap...

Page 88: ...tion The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disabled f1 f2 f3 0 disabled_fp_register_fault tmp_isrcode 0 i...

Page 89: ...e same register for FR f2 and FR f3 For the sign_form the sign of FR f2 is concatenated with the exponent and the significand of FR f3 For the sign_exp_form the sign and exponent of FR f2 is concatena...

Page 90: ...fp_is_natval FR f3 FR f1 NATVAL else FR f1 significand FR f3 significand if neg_sign_form FR f1 exponent FR f3 exponent FR f1 sign FR f2 sign else if sign_form FR f1 exponent FR f3 exponent FR f1 sign...

Page 91: ...ation The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disabled f1 f2 f3 0 disabled_fp_register_fault tmp_isrcode 0...

Page 92: ...ion value in FR f3 For all forms the exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and the sign field of FR f1 is set to positive 0 For all forms if either FR f2 or FR f3 is...

Page 93: ...R f2 significand 63 32 tmp_res_lo FR f3 significand 63 32 else if mix_r_form tmp_res_hi FR f2 significand 31 0 tmp_res_lo FR f3 significand 31 0 else mix_lr_form tmp_res_hi FR f2 significand 63 32 tmp...

Page 94: ...FPSR sf wre using the rounding mode specified by FPSR sf rc The rounded result is placed in FR f1 If either FR f3 or FR f4 is a NaTVal FR f1 is set to NaTVal instead of the computed result The mnemon...

Page 95: ...e 3 56 For the encodings and interpretation of the status field s pc wre and rc refer to Table 5 5 and Table 5 6 on page 1 90 Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disab...

Page 96: ...Volume 3 Instruction Reference 3 87 fms Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault Floating point Exception trap...

Page 97: ...nt Negate Format qp fneg f1 f3 pseudo op of qp fmerge ns f1 f3 f3 Description The value in FR f3 is negated and placed in FR f1 If FR f3 is a NaTVal FR f1 is set to NaTVal instead of the computed resu...

Page 98: ...lue Format qp fnegabs f1 f3 pseudo op of qp fmerge ns f1 f0 f3 Description The absolute value of the value in FR f3 is computed negated and placed in FR f1 If FR f3 is a NaTVal FR f1 is set to NaTVal...

Page 99: ...ble 2 23 on page 3 56 For the encodings and interpretation of the status field s pc wre and rc refer to Table 5 5 and Table 5 6 on page 1 90 Operation if PR qp fp_check_target_register f1 if tmp_isrco...

Page 100: ...Volume 3 Instruction Reference 3 91 fnma Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault Floating point Exception trap...

Page 101: ...sf pc and FPSR sf wre using the rounding mode specified by FPSR sf rc The rounded result is placed in FR f1 If either FR f3 or FR f4 is a NaTVal FR f1 is set to NaTVal instead of the computed result...

Page 102: ...ng the rounding mode specified by FPSR sf rc and placed in FR f1 If FR f3 is a NaTVal FR f1 is set to NaTVal instead of the computed result The mnemonic values for the opcode s pc are given in Table 2...

Page 103: ...field of FR f1 is set to positive 0 If either FR f2 or FR f3 is a NaTVal FR f1 is set to NaTVal instead of the computed result Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_dis...

Page 104: ...r of single precision values in the significand field of FR f3 are computed and stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and...

Page 105: ...FR f1 is set to NaTVal instead of the computed result Operation if PR qp fp_check_target_register f1 if tmp_isrcode fp_reg_disabled f1 f2 f3 0 disabled_fp_register_fault tmp_isrcode 0 if fp_is_natval...

Page 106: ...t instructions The Invalid Operation is signaled in the same manner as for the fpcmp lt operation The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_reg...

Page 107: ...uction Reference fpamax FP Exceptions Invalid Operation V Denormal Unnormal Operand D Software Assist SWA fault Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating p...

Page 108: ...tructions The Invalid Operation is signaled in the same manner as for the fpcmp lt operation The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register...

Page 109: ...uction Reference fpamin FP Exceptions Invalid Operation V Denormal Unnormal Operand D Software Assist SWA fault Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating p...

Page 110: ...mplemented in hardware Some are actually pseudo ops For these the assembler simply switches the source operand specifiers and or switches the predicate type specifiers and uses an implemented relation...

Page 111: ...lt tmp_rel fp_less_than tmp_fr2 tmp_fr3 else if frel nle tmp_rel fp_lesser_or_equal tmp_fr2 tmp_fr3 else if frel ngt tmp_rel fp_less_than tmp_fr3 tmp_fr2 else if frel nge tmp_rel fp_lesser_or_equal tm...

Page 112: ...p_res_hi tmp_res_lo FR f1 exponent FP_INTEGER_EXP FR f1 sign FP_SIGN_POSITIVE fp_update_fpsr sf tmp_fp_env fp_update_psr f1 FP Exceptions Invalid Operation V Denormal Unnormal Operand D Software Assis...

Page 113: ...r the rounding mode specified in the FPSR sf rc or using Round to Zero if the trunc_form of the instruction is used The result is written as a pair of 32 bit integers into the significand field of FR...

Page 114: ...INTEGER_EXP tmp_res exponent if signed_form tmp_res sign tmp_res significand tmp_res significand 1 tmp_res_hi tmp_res significand 31 0 if fp_is_nan tmp_default_result_pair lo tmp_res_lo INTEGER_INDEFI...

Page 115: ...3 106 Volume 3 Instruction Reference fpcvt fx Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault Floating point Exception trap...

Page 116: ...rc The pair of rounded results are stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and the sign field of FR f1 is set to positive...

Page 117: ...mp_res_hi fp_ieee_round_sp tmp_res HIGH tmp_fp_env if fp_is_nan_or_inf tmp_default_result_pair lo tmp_res_lo fp_single tmp_default_result_pair lo else tmp_res fp_mul fp_reg_read_lo f3 fp_reg_read_lo f...

Page 118: ...nvalid Operation is signaled in the same manner as for the fpcmp lt operation The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register f1 if tmp_isrc...

Page 119: ...3 110 Volume 3 Instruction Reference fpmax Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault...

Page 120: ...and the significands of the pair of single precision values in the significand field of FR f3 and stored in FR f1 For the sign_exp_form the signs and exponents of the pair of single precision values i...

Page 121: ...ificand 62 32 tmp_res_lo FR f2 significand 31 31 FR f3 significand 30 0 else sign_exp_form tmp_res_hi FR f2 significand 63 55 23 FR f3 significand 54 32 tmp_res_lo FR f2 significand 31 23 23 FR f3 sig...

Page 122: ...nvalid Operation is signaled in the same manner as for the fpcmp lt operation The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp fp_check_target_register f1 if tmp_isrc...

Page 123: ...3 114 Volume 3 Instruction Reference fpmin Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault...

Page 124: ...the rounding mode specified by FPSR sf rc The pair of rounded results are stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and the...

Page 125: ...rformed The mnemonic values for sf are given in Table 2 23 on page 3 56 The encodings and interpretation for the status field s rc are given in Table 5 6 on page 1 90 Operation if PR qp fp_check_targe...

Page 126: ...E fp_update_fpsr sf tmp_fp_env fp_update_psr f1 if fp_raise_traps tmp_fp_env fp_exception_trap fp_decode_trap tmp_fp_env FP Exceptions Invalid Operation V Underflow U Denormal Unnormal Operand D Overf...

Page 127: ...ecision values in the significand field of FR f3 are negated and stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and the sign field...

Page 128: ...e pair of single precision values in the significand field of FR f3 are computed negated and stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exponent for 2 06...

Page 129: ...ounded to single precision using the rounding mode specified by FPSR sf rc The pair of rounded results are stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exp...

Page 130: ...nv tmp_res_hi fp_ieee_round_sp tmp_res HIGH tmp_fp_env if fp_is_nan_or_inf tmp_default_result_pair lo tmp_res_lo fp_single tmp_default_result_pair lo else tmp_res fp_mul fp_reg_read_lo f3 fp_reg_read_...

Page 131: ...sion using the rounding mode specified by FPSR sf rc The pair of rounded results are stored in the significand field of FR f1 The exponent field of FR f1 is set to the biased exponent for 2 063 0x1003...

Page 132: ...llel frcpa instruction and merge the results into FR f1 keeping PR p2 cleared The exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and the sign field of FR f1 is set to positive...

Page 133: ...is_finite den tmp_res FP_INFINITY tmp_res sign num sign den sign tmp_pred_lo 0 else if fp_is_finite num fp_is_inf den tmp_res FP_ZERO tmp_res sign num sign den sign tmp_pred_lo 0 else if fp_is_zero nu...

Page 134: ...ume 3 Instruction Reference 3 125 fprcpa Denormal Unnormal Operand D Software Assist SWA fault Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fau...

Page 135: ...hen PR p2 is cleared user software is expected to compute the square root for each half using the non parallel frsqrta instruction and merge the results in FR f1 keeping PR p2 cleared The exponent fie...

Page 136: ...s_pos_inf tmp_fr3 tmp_res FP_ZERO tmp_pred_lo 0 else tmp_res fp_ieee_recip_sqrt tmp_fr3 if limits_check lo tmp_pred_lo 0 else tmp_pred_lo 1 tmp_res_lo fp_single tmp_res FR f1 significand fp_concatenat...

Page 137: ...e is expected to compute the IEEE 754 quotient FR f2 FR f3 return the result in FR f1 and set PR p2 to 0 If either FR f2 or FR f3 is a NaTVal FR f1 is set to NaTVal instead of the computed result and...

Page 138: ...19e 0x19a 0x197 0x193 0x18f 0x18b 0x187 0x183 0x17f 0x17c 0x178 0x174 0x171 0x16d 0x169 0x166 0x162 0x15e 0x15b 0x157 0x154 0x150 0x14d 0x149 0x146 0x142 0x13f 0x13b 0x138 0x134 0x131 0x12e 0x12a 0x12...

Page 139: ...ce frcpa return tmp_res FP Exceptions Invalid Operation V Zero Divide Z Denormal Unnormal Operand D Software Assist SWA fault Interruptions Illegal Operation fault Floating point Exception fault Disab...

Page 140: ...54 square root result then a Floating point Exception fault for Software Assist occurs System software is expected to compute the IEEE 754 square root return the result in FR f1 and set PR p2 to 0 If...

Page 141: ...7 0x005 0x003 0x001 0x3fc 0x3f4 0x3ec 0x3e5 0x3dd 0x3d5 0x3ce 0x3c7 0x3bf 0x3b8 0x3b1 0x3aa 0x3a3 0x39c 0x395 0x38e 0x388 0x381 0x37a 0x374 0x36d 0x367 0x361 0x35a 0x354 0x34e 0x348 0x342 0x33c 0x336...

Page 142: ...Volume 3 Instruction Reference 3 133 frsqrta Interruptions Illegal Operation fault Floating point Exception fault Disabled Floating point Register fault...

Page 143: ...to the biased exponent for 2 063 0x1003E The sign bit field of FR f1 is set to positive 0 If any of FR f3 FR f4 or FR f2 is a NaTVal FR f1 is set to NaTVal instead of the computed result Operation if...

Page 144: ...lly AND ing the sf0 controls and amask7 immediate field and logically OR ing the omask7 immediate field The mnemonic values for sf are given in Table 2 23 on page 3 56 Operation if PR qp tmp_controls...

Page 145: ...f wre using the rounding mode specified by FPSR sf rc and placed in FR f1 If either FR f3 or FR f2 is a NaTVal FR f1 is set to NaTVal instead of the computed result The mnemonic values for the opcode...

Page 146: ...n value is negated For the swap_nr_form the left single precision value in FR f2 is concatenated with the right single precision value in FR f3 The concatenated pair is then swapped and the right sing...

Page 147: ...cand 31 31 FR f3 significand 30 0 tmp_res_lo FR f2 significand 63 32 else swap_nr_form tmp_res_hi FR f3 significand 31 0 tmp_res_lo FR f2 significand 63 31 FR f2 significand 62 32 FR f1 significand fp...

Page 148: ...FR f3 For all forms the exponent field of FR f1 is set to the biased exponent for 2 063 0x1003E and the sign field of FR f1 is set to positive 0 For all forms if either FR f2 or FR f3 is a NaTVal FR...

Page 149: ...f sxt_l_form tmp_res_hi FR f2 significand 63 0xFFFFFFFF 0x00000000 tmp_res_lo FR f3 significand 63 32 else sxt_r_form tmp_res_hi FR f2 significand 31 0xFFFFFFFF 0x00000000 tmp_res_lo FR f3 significand...

Page 150: ...of any prior stores is completed An fwb instruction does not ensure ordering of stores since later stores may be flushed before prior stores To ensure prior coalesced stores are made visible before la...

Page 151: ...e sign field of FR f1 is set to positive 0 If either of FR f2 or FR f3 is a NaTVal FR f1 is set to NaTVal instead of the computed result Operation if PR qp fp_check_target_register f1 if tmp_isrcode f...

Page 152: ...Figure 5 8 on page 1 95 respectively In the single_form the most significant 32 bits of GR r1 are set to 0 In the exponent_form the exponent field of FR f2 is copied to bits 16 0 of GR r1 and the sig...

Page 153: ...le_form GR r1 31 0 fp_fr_to_mem_format FR f2 4 0 GR r1 63 32 0 else if double_form GR r1 fp_fr_to_mem_format FR f2 8 0 else if exponent_form GR r1 63 18 0 GR r1 16 0 FR f2 exponent GR r1 17 FR f2 sign...

Page 154: ...inning or performing low priority tasks This hint can be used by the processor to allocate more resources or time to another executing stream on the same processor For the case where the currently exe...

Page 155: ...are invalidated In the complete_form all ALAT entries are invalidated In the entry_form the ALAT is queried using the general register specifier r1 gr_form or the floating point register specifier f1...

Page 156: ...algorithm The visibility of the itc instruction to externally generated purges ptc g ptc ga must occur before subsequent memory operations From a software perspective this is similar to acquire semant...

Page 157: ...entries tmp_rid tmp_va tmp_size slot tlb_replacement_algorithm ITC_TYPE tlb_insert_inst slot GR r2 CR ITIR CR IFA tmp_rid TC else data_form tlb_must_purge_dtc_entries tmp_rid tmp_va tmp_size tlb_may_p...

Page 158: ...plicit ptr instructions before inserting the new TR entry This instruction can only be executed at the most privileged level and when PSR ic and PSR vm are both 0 Operation if PR qp if PSR ic illegal_...

Page 159: ...n instruction serialization operation before a dependent instruction fetch access For the data_form software must issue a data serialization operation before issuing a data access or non access refere...

Page 160: ...form are none and acq For the fill_form an 8 byte value is loaded and a bit in the UNAT application register is copied into the target register NaT bit This instruction is used for reloading a spilled...

Page 161: ...eptions may be deferred Deferral causes the target register s NaT bit to be set and the processor ensures that no ALAT entry exists for the target register The absence of an ALAT entry is later used t...

Page 162: ...aTPage is optional On processor models that do not support such ld16 accesses an Unsupported Data Reference fault is raised when an unsupported reference is attempted For the sixteen_byte_form Illegal...

Page 163: ...r3 illegal_operation_fault check_target_register r1 if reg_base_update_form imm_base_update_form check_target_register r3 if reg_base_update_form tmp_r2 GR r2 tmp_r2nat GR r2 nat if speculative GR r3...

Page 164: ...fill NaT on ld8 fill bit_pos GR r3 8 3 GR r1 val GR r1 nat AR UNAT bit_pos else clear NaT on other types if size 16 GR r1 val AR CSD val_ar else GR r1 zero_ext val size 8 GR r1 nat 0 if check_no_clea...

Page 165: ...umption fault Data Key Miss fault Unimplemented Data Address fault Data Key Permission fault Data Nested TLB fault Data Access Rights fault Alternate Data TLB fault Data Access Bit fault VHPT Data fau...

Page 166: ...he fill_form a 16 byte value is loaded and the appropriate fields are placed in FR f1 without conversion This instruction is used for reloading a spilled register See Section 4 4 4 Control Speculation...

Page 167: ...a cacheable page with write back policy nor a NaTPage is optional On processor models that do not support such ldfe accesses an Unsupported Data Reference fault is raised when an unsupported referenc...

Page 168: ...PSR ed defer exception if spec if check alat_cmp FLOAT f1 translate_address alat_translate_address_on_hit fldtype FLOAT f1 read_memory alat_read_memory_on_hit fldtype FLOAT f1 if translate_address if...

Page 169: ...GR r3 ldhint itype fp_update_psr f1 Interruptions Illegal Operation fault Data NaT Page Consumption fault Disabled Floating point Register fault Data Key Miss fault Register NaT Consumption fault Data...

Page 170: ...ue in GR r3 is added to an implied immediate value equal to double the data size and the result is placed back in GR r3 This base register update is done after the load and does not affect the load ad...

Page 171: ...fault on NaT address register_nat_consumption_fault itype defer speculative GR r3 nat PSR ed defer exception if spec if check alat_cmp FLOAT f1 translate_address alat_translate_address_on_hit fldtype...

Page 172: ...register GR r3 GR r3 size GR r3 nat GR r3 nat if GR r3 nat mem_implicit_prefetch GR r3 ldhint itype fp_update_psr f1 fp_update_psr f2 Interruptions Illegal Operation fault Data Page Not Present fault...

Page 173: ...e completer lftype specifies whether or not the instruction raises faults normally associated with a regular load Table 2 37 defines these two options In the base update forms after being used to addr...

Page 174: ...ndled invisibly e g if handling the fault would involve terminating the program the OS must return to the interrupted program skipping over the data prefetch This can easily be done by setting the IPS...

Page 175: ...if defer mem_promote paddr mattr lfhint excl_hint if imm_base_update_form GR r3 GR r3 sign_ext imm9 9 GR r3 nat GR r3 nat else if reg_base_update_form GR r3 GR r3 GR r2 GR r3 nat GR r2 nat GR r3 nat...

Page 176: ...on will fault with an Illegal Operation fault under any of the following conditions the RSE is not in enforced lazy mode RSC mode is non zero CFM sof and RSC loadrs are both non zero an attempt is mad...

Page 177: ...prevents any subsequent data memory accesses by the processor from initiating transactions to the external platform until all prior loads to sequential pages have returned data and all prior stores t...

Page 178: ...x4 r r1 r2 r3 four_byte_form right_form I2 Description The data elements of GR r2 and r3 are mixed as shown in Figure 2 25 and the result placed in GR r1 The data elements in the source registers are...

Page 179: ...lume 3 Instruction Reference mix Figure 2 25 Mix Examples GR r2 GR r1 GR r3 mix1 l GR r2 GR r1 GR r3 GR r2 GR r1 GR r3 GR r2 GR r1 GR r3 mix1 r GR r2 GR r1 GR r3 mix2 l mix2 r GR r2 GR r1 GR r3 mix4 l...

Page 180: ...x 7 y 7 x 5 y 5 x 3 y 3 x 1 y 1 else right_form GR r1 concatenate8 x 6 y 6 x 4 y 4 x 2 y 2 x 0 y 0 else if two_byte_form two byte elements x 0 GR r2 15 0 y 0 GR r3 15 0 x 1 GR r2 31 16 y 1 GR r3 31 1...

Page 181: ...n extended value in imm8 in the immediate_form is placed in AR ar3 In the register_form if the NaT bit corresponding to GR r2 is set then a Register NaT Consumption fault is raised Only a subset of th...

Page 182: ...ar3 BSPSTORE ar3 RNAT AR RSC mode 0 illegal_operation_fault if register_form GR r2 nat register_nat_consumption_fault 0 if is_reserved_field AR_TYPE ar3 tmp_val reserved_register_field_fault if is_ke...

Page 183: ...he value being moved into BR b1 The return_form is used to provide the hint that this value will be used in a return type branch The values for the mwh whether hint completer are given in Table 2 39 F...

Page 184: ...Operation fault Operation if PR qp if is_reserved_reg CR_TYPE cr3 to_form is_read_only_reg CR_TYPE cr3 PSR ic is_interruption_cr cr3 illegal_operation_fault if from_form check_target_register r1 if P...

Page 185: ...fault Serialization Reads of control registers reflect the results of all prior instruction groups and interruptions In general writes to control registers do not immediately affect subsequent instruc...

Page 186: ...on Reference 3 177 mov fr mov Move Floating point Register Format qp mov f1 f3 pseudo op of qp fmerge s f1 f3 f3 Description The value of FR f3 is copied to FR f1 Operation See fmerge Floating point M...

Page 187: ...178 Volume 3 Instruction Reference mov gr mov Move General Register Format qp mov r1 r3 pseudo op of qp adds r1 0 r3 Description The value of GR r3 is copied to GR r1 Operation See add Add on page 3 1...

Page 188: ...Reference 3 179 mov imm mov Move Immediate Format qp mov r1 imm22 pseudo op of qp addl r1 imm22 r0 Description The immediate value imm22 is sign extended to 64 bits and placed in GR r1 Operation See...

Page 189: ...U identification registers can only be read There is no to_form of this instruction For move to protection key register the processor ensures uniqueness of protection keys by checking new valid protec...

Page 190: ...x break case PKR_TYPE GR r1 PKR tmp_index break case PMC_TYPE GR r1 pmc_read tmp_index break case RR_TYPE GR r1 RR tmp_index break GR r1 nat 0 else to_form if PSR cpl 0 privileged_operation_fault 0 if...

Page 191: ...g a memory reference dependent on the modified register For move to instruction breakpoint registers software must issue an instruction serialize operation before fetching an instruction dependent on...

Page 192: ...e Instruction Pointer Format qp mov r1 ip I25 Description The Instruction Pointer IP for the bundle containing this instruction is copied into GR r1 Operation if PR qp check_target_register r1 GR r1 I...

Page 193: ...erred exception for GR r2 the NaT bit is 1 a Register NaT Consumption fault is taken In the to_rotate_form only the 48 rotating predicates can be written The source operand is taken from the imm44 ope...

Page 194: ...vm is 0 The contents of the interruption resources that are overwritten when the PSR ic bit is 1 are undefined if an interruption occurs between the enabling of the PSR ic bit and a subsequent instruc...

Page 195: ...ise PSR up is not modified Writing a non zero value into any other parts of the PSR results in a Reserved Register Field fault Operation if PR qp if from_form check_target_register r1 GR r1 zero_ext P...

Page 196: ...ng Immediate Format qp movl r1 imm64 X2 Description The immediate value imm64 is copied to GR r1 The L slot of the bundle contains 41 bits of imm64 Operation if PR qp check_target_register r1 GR r1 im...

Page 197: ...ands are treated as unsigned values and are multiplied and the result is placed in GR r1 The upper 32 bits of each of the source operands are ignored Operation if PR qp if instruction_implemented mpy4...

Page 198: ...s of GR r2 and the upper 32 bits of GR r3 are ignored This instruction can be used to perform a 64 bit integer multiply operation producing a 64 bit result rc ra rb mpy4 r1 ra rb partial product low 3...

Page 199: ...iven in Table 2 41 and shown in Figure 2 26 Table 2 41 Mux Permutations for 8 bit Elements mbtype4 Function rev Reverse the order of the bytes mix Perform a Mix operation on the two halves of GR r2 sh...

Page 200: ...pied to corresponding 16 bit positions in the target register GR r1 The indices are encoded in little endian order The 8 bits of mhtype8 7 0 are grouped in pairs of bits and named mhtype8 3 mhtype8 2...

Page 201: ...r1 concatenate8 x 7 x 3 x 5 x 1 x 6 x 2 x 4 x 0 break case shuf GR r1 concatenate8 x 7 x 3 x 6 x 2 x 5 x 1 x 4 x 0 break case alt GR r1 concatenate8 x 7 x 5 x 3 x 1 x 6 x 4 x 2 x 0 break case brcst G...

Page 202: ...m62 can be used by software as a marker in program code It is ignored by hardware For the x_unit_form the L slot of the bundle contains the upper 41 bits of imm62 A nop i instruction may be encoded in...

Page 203: ...y ORed and the result placed in GR r1 In the register form the first operand is GR r2 in the immediate form the first operand is taken from the imm8 encoding field Operation if PR qp check_target_regi...

Page 204: ...source element cannot be represented in the result element then saturation clipping is performed The saturation can either be signed or unsigned If an element is larger than the upper limit value the...

Page 205: ...6 16 temp 6 sign_ext GR r3 47 32 16 temp 7 sign_ext GR r3 63 48 16 for i 0 i 8 i if temp i max temp i max if temp i min temp i min GR r1 concatenate8 temp 7 temp 6 temp 5 temp 4 temp 3 temp 2 temp 1 t...

Page 206: ...epresented in the result element and a saturation completer is specified then saturation clipping is performed The saturation can either be signed or unsigned as given in Table 2 43 If the sum of two...

Page 207: ...xt 0x80 8 for i 0 i 8 i temp i sign_ext x i 8 sign_ext y i 8 else if uus_saturation_form max 0xff min 0x00 for i 0 i 8 i temp i zero_ext x i 8 sign_ext y i 8 else if uuu_saturation_form max 0xff min 0...

Page 208: ...uration_form max 0xffff min 0x0000 for i 0 i 4 i temp i zero_ext x i 16 zero_ext y i 16 else modulo_form for i 0 i 4 i temp i zero_ext x i 16 zero_ext y i 16 if sss_saturation_form uus_saturation_form...

Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...

Page 210: ...bit position The high order bits of each element are filled with the carry bits of the sums To prevent cumulative round off errors an averaging is performed The unsigned results are placed in GR r1 T...

Page 211: ...ume 3 Instruction Reference pavg Figure 2 31 Parallel Average with Round Away from Zero Example GR r2 GR r1 GR r3 pavg2 raz Sum Bits Carry Bit 1 1 1 1 16 bit Sum Plus Carry Shift Right 1 Bit Shift Rig...

Page 212: ...else normal form for i 0 i 8 i temp i zero_ext x i 8 zero_ext y i 8 res i shift_right_unsigned temp i 1 temp i 0 GR r1 concatenate8 res 7 res 6 res 5 res 4 res 3 res 2 res 1 res 0 else two_byte_form x...

Page 213: ...position The high order bits of each element are filled with the borrow bits of the subtraction the complements of the ALU carries To prevent cumulative round off errors an averaging is performed The...

Page 214: ...8 x 7 GR r2 63 56 y 7 GR r3 63 56 for i 0 i 8 i temp i zero_ext x i 8 zero_ext y i 8 res i temp i 8 0 u 1 temp i 0 GR r1 concatenate8 res 7 res 6 res 5 res 4 res 3 res 2 res 1 res 0 else two_byte_form...

Page 215: ...R r2 and GR r3 then the corresponding data element in GR r1 is set to all ones If the comparison condition is false then the corresponding data element in GR r1 is set to all zeros For the relation bo...

Page 216: ...tmp_rel res i 0xff else res i 0x00 GR r1 concatenate8 res 7 res 6 res 5 res 4 res 3 res 2 res 1 res 0 else if two_byte_form two byte elements x 0 GR r2 15 0 y 0 GR r3 15 0 x 1 GR r2 31 16 y 1 GR r3 3...

Page 217: ...3 208 Volume 3 Instruction Reference pcmp else res i 0x00000000 GR r1 concatenate2 res 1 res 0 GR r1 nat GR r2 nat GR r3 nat Interruptions Illegal Operation fault...

Page 218: ...r2 is compared with the corresponding unsigned 8 bit element of GR r3 and the greater of the two is placed in the corresponding 8 bit element of GR r1 In the two_byte_form each signed 16 bit element...

Page 219: ...6 GR r2 55 48 y 6 GR r3 55 48 x 7 GR r2 63 56 y 7 GR r3 63 56 for i 0 i 8 i res i zero_ext x i 8 zero_ext y i 8 y i x i GR r1 concatenate8 res 7 res 6 res 5 res 4 res 3 res 2 res 1 res 0 else two byt...

Page 220: ...r2 is compared with the corresponding unsigned 8 bit element of GR r3 and the smaller of the two is placed in the corresponding 8 bit element of GR r1 In the two_byte_form each signed 16 bit element...

Page 221: ...6 GR r2 55 48 y 6 GR r3 55 48 x 7 GR r2 63 56 y 7 GR r3 63 56 for i 0 i 8 i res i zero_ext x i 8 zero_ext y i 8 x i y i GR r1 concatenate8 res 7 res 6 res 5 res 4 res 3 res 2 res 1 res 0 else two byt...

Page 222: ...2 bit results are placed in GR r1 Operation if PR qp check_target_register r1 if right_form GR r1 31 0 sign_ext GR r2 15 0 16 sign_ext GR r3 15 0 16 GR r1 63 32 sign_ext GR r2 47 32 16 sign_ext GR r3...

Page 223: ...is then shifted to the right count2 bits and the least significant 16 bits of each shifted product form 4 16 bit results which are placed in GR r1 A count2 of 0 gives the 16 low bits of the results a...

Page 224: ...r2 47 32 y 2 GR r3 47 32 x 3 GR r2 63 48 y 3 GR r3 63 48 for i 0 i 4 i if unsigned_form unsigned multiplication temp i zero_ext x i 16 zero_ext y i 16 else signed multiplication temp i sign_ext x i 16...

Page 225: ...r3 I9 Description The number of bits in GR r3 having the value 1 is counted and the resulting sum is placed in GR r1 Operation if PR qp check_target_register r1 res 0 Count up all the one bits for i 0...

Page 226: ...bits 60 0 and the region register indexed by GR r3 bits 63 61 is permitted at the privilege level given by either GR r2 bits 1 0 or imm2 If PSR pk is 1 protection key checks are also performed The rea...

Page 227: ...obe Instructions Probe Form Type Faults regular_form Register NaT Consumption fault Virtualization faulta Data Nested TLB fault Alternate Data TLB fault VHPT Data fault Data TLB fault Data Page Not Pr...

Page 228: ...f fault_form tlb_translate GR r3 1 itype tmp_pl mattr defer else regular_form if impl_probe_intercept check_probe_virtualization_fault itype tmp_pl GR r1 tlb_grant_permission GR r3 itype tmp_pl GR r1...

Page 229: ...Description The unsigned 8 bit elements of GR r2 are subtracted from the unsigned 8 bit elements of GR r3 The absolute value of each difference is accumulated across the elements and placed in GR r1 F...

Page 230: ...r2 23 16 y 2 GR r3 23 16 x 3 GR r2 31 24 y 3 GR r3 31 24 x 4 GR r2 39 32 y 4 GR r3 39 32 x 5 GR r2 47 40 y 5 GR r3 47 40 x 6 GR r2 55 48 y 6 GR r3 55 48 x 7 GR r2 63 56 y 7 GR r3 63 56 GR r1 0 for i 0...

Page 231: ...r than 15 for 16 bit quantities or 31 for 32 bit quantities yield all zero results The results are placed in GR r1 Operation if PR qp check_target_register r1 shift_count variable_form GR r3 count5 tm...

Page 232: ...s a signed 16 bit value the final result is saturated The four signed 16 bit results are placed in GR r1 The first operand can be shifted by 1 2 or 3 bits Operation if PR qp check_target_register r1 x...

Page 233: ...ble_form I5 qp pshr4 u r1 r3 count5 unsigned_form four_byte_form fixed_form I6 Description The data elements of GR r3 are each independently shifted to the right by the scalar shift count in GR r2 or...

Page 234: ...ount else signed shift GR r1 15 0 shift_right_signed sign_ext GR r3 15 0 16 shift_count GR r1 31 16 shift_right_signed sign_ext GR r3 31 16 16 shift_count GR r1 47 32 shift_right_signed sign_ext GR r3...

Page 235: ...2 The add operation is performed with signed saturation The four signed 16 bit results of the add are placed in GR r1 The first operand can be shifted by 1 2 or 3 bits Operation if PR qp check_target_...

Page 236: ...represented in the result element and a saturation completer is specified then saturation clipping is performed The saturation can either be signed or unsigned as given in Table 2 48 If the difference...

Page 237: ...if uus_saturation_form uus_saturation_form max 0xff min 0x00 for i 0 i 8 i temp i zero_ext x i 8 sign_ext y i 8 else if uuu_saturation_form uuu_saturation_form max 0xff min 0x00 for i 0 i 8 i temp i...

Page 238: ...i 4 i temp i zero_ext x i 16 zero_ext y i 16 else modulo_form for i 0 i 4 i temp i zero_ext x i 16 zero_ext y i 16 if sss_saturation_form uus_saturation_form uuu_saturation_form for i 0 i 4 i if temp...

Page 239: ...ll processor models Software can acquire parameters through a processor dependent layer that is accessed through a procedural interface The selected region registers must remain unchanged during the l...

Page 240: ...c g must be the last instruction in an instruction group otherwise its behavior including its ordering semantics is undefined The behavior of the ptc ga instruction is similar to ptc g In addition to...

Page 241: ...n fault Register NaT Consumption fault Serialization The broadcast purge TC is not synchronized with the instruction stream on a remote processor Software cannot depend on any such synchronization wit...

Page 242: ...ranslation cache This instruction can only be executed at the most privileged level and when PSR vm is 0 This is a local operation no purge broadcast to other processors occurs in a multiprocessor sys...

Page 243: ...he purge In addition in both forms the instruction and data translation cache may be purged of more translations than specified by the purge parameters up to and including removal of all entries withi...

Page 244: ...e tlb_may_purge_itc_entries tmp_rid tmp_va tmp_size else instruction_form tlb_must_purge_itr_entries tmp_rid tmp_va tmp_size tlb_must_purge_itc_entries tmp_rid tmp_va tmp_size tlb_may_purge_dtc_entrie...

Page 245: ...s instruction can only be executed at the most privileged level and when PSR vm is 0 This instruction can not be predicated Execution of this instruction is undefined if PSR ic or PSR i are 1 Software...

Page 246: ...EFLAG rf and PSR id are unmodified until the successful completion of the target IA 32 instruction PSR da PSR dd PSR ia and PSR ed are cleared to zero before the target IA 32 instruction begins execu...

Page 247: ...ate CR IFS ifm sof 0 rse_restore_frame CR IFS ifm sof tmp_growth CFM sof CFM CR IFS ifm rse_enable_current_frame_load IP tmp_IP instruction_serialize if unimplemented_address unimplemented_instruction...

Page 248: ...ediately following the rsm instruction If the qualifying predicate of the rsm is false then external interrupts may be disabled until the next data serialization operation that follows the rsm instruc...

Page 249: ...ualization fault Reserved Register Field fault Serialization Software must use a data serialize or instruction serialize operation before issuing instructions dependent upon the altered PSR bits excep...

Page 250: ...SR up is only cleared if the secure performance monitor bit PSR sp is zero Otherwise PSR up is not modified Operation if PR qp if is_reserved_field PSR_TYPE PSR_UM imm24 reserved_register_field_fault...

Page 251: ...re 5 5 on page 1 93 respectively In the exponent_form bits 16 0 of GR r2 are copied to the exponent field of FR f1 and bit 17 of GR r2 is copied to the sign bit of FR f1 The significand field of FR f1...

Page 252: ...rm FR f1 fp_mem_to_fr_format GR r2 4 0 else if double_form FR f1 fp_mem_to_fr_format GR r2 8 0 else if significand_form FR f1 significand GR r2 FR f1 exponent FP_INTEGER_EXP FR f1 sign 0 else exponent...

Page 253: ...nd placed in GR r1 The number of bit positions to shift is specified by the value in GR r3 or by an immediate value count6 The shift count is interpreted as an unsigned number If the value in GR r3 is...

Page 254: ...first source operand is shifted to the left by count2 bits and then added to the second source operand and the result placed in GR r1 The first operand can be shifted by 1 2 3 or 4 bits Operation if P...

Page 255: ...s of the result are forced to zero and then bits 31 30 of GR r3 are copied to bits 62 61 of the result This result is placed in GR r1 The first operand can be shifted by 1 2 3 or 4 bits Operation if P...

Page 256: ...to shift is specified by the value in GR r2 or by an immediate value count6 The shift count is interpreted as an unsigned number If the value in GR r2 is greater than 63 then the result is all zeroes...

Page 257: ...he right count6 bits The least significant 64 bits of the result are placed in GR r1 The immediate value count6 can be any number in the range 0 to 63 Operation if PR qp check_target_register r1 temp1...

Page 258: ...must be in an instruction group after the instruction group containing the srlz i Data serialization srlz d ensures prior modifications to processor register resources that affect subsequent executio...

Page 259: ...SR_SM imm24 reserved_register_field_fault if PSR vm 1 virtualization_fault if imm24 1 PSR 1 1 be if imm24 2 PSR 2 1 up if imm24 3 PSR 3 1 ac if imm24 4 PSR 4 1 mfl if imm24 5 PSR 5 1 mfh if imm24 13 P...

Page 260: ...ction is used for spilling a register NaT pair See Section 4 4 4 Control Speculation on page 1 60 for details In the imm_base_update form the value in GR r3 is added to a signed immediate value imm9 a...

Page 261: ...GR r3 size itype PSR cpl mattr tmp_unused if spill_form GR r2 nat natd_gr_write GR r2 paddr size UM be mattr otype sthint else if sixteen_byte_form mem_write16 GR r2 AR CSD paddr UM be mattr otype st...

Page 262: ...Volume 3 Instruction Reference 3 253 st Data TLB fault Unaligned Data Reference fault Data Page Not Present fault Unsupported Data Reference fault Data NaT Page Consumption fault...

Page 263: ...format In the spill_form a 16 byte value from FR f2 is stored without conversion This instruction is used for spilling a register See Section 4 4 4 Control Speculation on page 1 60 for details In the...

Page 264: ...te val paddr size UM be mattr UNORDERED sthint alat_inval_multiple_entries paddr size if imm_base_update_form GR r3 GR r3 sign_ext imm9 9 GR r3 nat 0 mem_implicit_prefetch GR r3 sthint WRITE Interrupt...

Page 265: ...register form the first operand is GR r2 in the immediate form the first operand is taken from the sign extended imm8 encoding field The minus1_form is available only in the register_form although th...

Page 266: ...nly be set if the secure performance monitor bit PSR sp is zero Otherwise PSR up is not modified Operation if PR qp if is_reserved_field PSR_TYPE PSR_UM imm24 reserved_register_field_fault if imm24 1...

Page 267: ...ded from the bit position specified by xsz and the result is placed in GR r1 The mnemonic values for xsz are given in Table 2 52 Operation if PR qp check_target_register r1 GR r1 sign_ext GR r3 xsz 8...

Page 268: ...the programmer must explicitly insert ordered data references acquire release or fence type to appropriately constrain sync i and hence fc and fc i visibility to the data stream on other processors sy...

Page 269: ...ified by GR r3 the value 1 is returned When PSR dt is 0 only the DTLB is searched because the VHPT walker is disabled If no matching present translation is found in the DTLB the value 1 is returned A...

Page 270: ...and zero sense of the test For normal and unc types only the z value is directly implemented in hardware the nz value is actually a pseudo op For it the assembler simply switches the predicate target...

Page 271: ...e if GR r3 nat tmp_rel PR p1 0 PR p2 0 break case or or type compare if GR r3 nat tmp_rel PR p1 1 PR p2 1 break case or andcm or andcm type compare if GR r3 nat tmp_rel PR p1 1 PR p2 0 break case unc...

Page 272: ...e test For normal and unc types only the z value is directly implemented in hardware the nz value is actually a pseudo op For it the assembler simply switches the predicate target specifiers and uses...

Page 273: ...el tmp_rel switch ctype case and and type compare if tmp_rel PR p1 0 PR p2 0 break case or or type compare if tmp_rel PR p1 1 PR p2 1 break case or andcm or andcm type compare if tmp_rel PR p1 1 PR p2...

Page 274: ...implementation specific long format hash function on the virtual address to generate a hash index into the long format VHPT In the long format a translation in the VHPT must be uniquely identified by...

Page 275: ...normal and unc types only the z value is directly implemented in hardware the nz value is actually a pseudo op For it the assembler simply switches the predicate target specifiers and uses the implem...

Page 276: ...ctype case and and type compare if tmp_rel PR p1 0 PR p2 0 break case or or type compare if tmp_rel PR p1 1 PR p2 1 break case or andcm or andcm type compare if tmp_rel PR p1 1 PR p2 0 break case unc...

Page 277: ...slation is found in the DTLB an Alternate Data TLB fault is raised if psr ic is one or a Data Nested TLB fault is raised if psr ic is zero If this instruction faults then it will set the non access bi...

Page 278: ...eneration function must use all implemented region bits and only virtual address bits 60 0 PTA vf is ignored by this instruction A translation in the long format VHPT must be uniquely identified by it...

Page 279: ...te_form low_form I2 qp unpack2 l r1 r2 r3 two_byte_form low_form I2 qp unpack4 l r1 r2 r3 four_byte_form low_form I2 Description The data elements of GR r2 and r3 are unpacked and the result placed in...

Page 280: ...Reference 3 271 unpack Figure 2 45 Unpack Operation GR r2 GR r1 GR r3 unpack1 h GR r2 GR r1 GR r3 GR r2 GR r1 GR r3 GR r2 GR r1 GR r3 unpack1 l GR r2 GR r1 GR r3 unpack2 h unpack2 l GR r2 GR r1 GR r3...

Page 281: ...ate8 x 7 y 7 x 6 y 6 x 5 y 5 x 4 y 4 else low_form GR r1 concatenate8 x 3 y 3 x 2 y 2 x 1 y 1 x 0 y 0 else if two_byte_form two byte elements x 0 GR r2 15 0 y 0 GR r3 15 0 x 1 GR r2 31 16 y 1 GR r3 31...

Page 282: ...PSR vm Instructions in subsequent instruction groups will be executed with PSR vm equal to the new value If the above conditions are not met this instruction takes a Virtualization fault This instruc...

Page 283: ...rite access privileges for the referenced page are required The exchange is performed with acquire semantics i e the memory read write is made visible prior to all subsequent data memory accesses See...

Page 284: ...mattr ACQUIRE ldhint alat_inval_multiple_entries paddr sz GR r1 zero_ext val sz 8 GR r1 nat 0 Interruptions Illegal Operation fault Data Key Miss fault Register NaT Consumption fault Data Key Permissi...

Page 285: ...in the significand field of FR f1 In the high_form the significand fields of FR f3 and FR f4 are treated as signed integers and multiplied to produce a full 128 bit signed result The significand fiel...

Page 286: ...tmp_res_128 fp_I64_x_I64_to_I128 FR f3 significand FR f4 significand else high_unsigned_form tmp_res_128 fp_U64_x_U64_to_U128 FR f3 significand FR f4 significand tmp_res_128 fp_U128_add tmp_res_128 f...

Page 287: ...ficant 64 bits of the resultant product are placed in the significand field of FR f1 In the high_form the significand fields of FR f3 and FR f4 are treated as signed integers and multiplied to produce...

Page 288: ...ically XORed and the result placed in GR r1 In the register_form the first operand is GR r2 in the imm8_form the first operand is taken from the imm8 encoding field Operation if PR qp check_target_reg...

Page 289: ...value in GR r3 is zero extended above the bit position specified by xsz and the result is placed in GR r1 The mnemonic values for xsz are given in Table 2 52 on page 3 258 Operation if PR qp check_tar...

Page 290: ...t_inval_multiple_entries paddr size The ALAT is queried using the physical memory address specified by paddr and the access size specified by size All matching ALAT entries are invalidated No value is...

Page 291: ...sum ready for rounding fcmp_exception_fault_check f2 f3 frel sf tmp_fp_env Checks for all floating point faulting conditions for the fcmp instruction fcvt_fx_exception_fault_check fr2 signed_form tru...

Page 292: ...sr sf tmp_fp_env Copies a floating point instruction s local state into the global FPSR fp_update_psr dest_freg Conditionally sets PSR mfl or PSR mfh based on dest_freg fpcmp_exception_fault_check f2...

Page 293: ...ation specific function indicates whether probe interceptions are supported impl_ruc Implementation specific function which indicates whether Resource Utilization Counter RUC application register is i...

Page 294: ...y attributes specified by mattr and access hint specified by hint otype specifies the memory ordering attribute of this access and must be UNORDERED or ACQUIRE mem_read_pair low_value high_value paddr...

Page 295: ...ordering only affects the ordering of bytes within each of the 8 byte values stored otype specifies the memory ordering attribute of this access and has the value ACQUIRE or RELEASE ordering_fence Ens...

Page 296: ...s by how many registers the top of the current frame will grow growth will generally be negative The number of registers specified by preserved_sol are marked to be restored Register renaming causes t...

Page 297: ...e access rights and the privilege level assigned to the page is higher than numerically less than the current privilege level then the current privilege level is set to the privilege level field in th...

Page 298: ...e tlb_must_purge_itc_entries rid vaddr size Purges all local possibly overlapping ITC entry matching the specified region identifier rid virtual address vaddr and page size size vaddr 63 61 VRN is ign...

Page 299: ...lt is generated tlb_translate_nonaccess does not return The following faults are checked Unimplemented Data Address fault Virtualization fault tpa only Data Nested TLB fault Alternate Data TLB fault V...

Page 300: ...t and virtual machine features are disabled See Section 3 4 Processor Virtualization on page 2 44 in SDM and PAL_PROC_GET_FEATURES Get Processor Dependent Features 17 on page 2 446 in SDM for details...

Page 301: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3...

Page 302: ...for each encoding of the template field A double line to the right of an instruction slot indicates that a stop occurs at that point within the current bundle See Instruction Encoding Overview on page...

Page 303: ...ield Encoding and Instruction Slot Mapping Template Slot 0 Slot 1 Slot 2 00 M unit I unit I unit 01 M unit I unit I unit 02 M unit I unit I unit 03 M unit I unit I unit 04 M unit L unit X unita 05 M u...

Page 304: ...n field names used throughout this chapter are described in Table 4 6 on page 3 298 The set of special notations such as whether an instruction is privileged are listed in Table 4 7 on page 3 299 Thes...

Page 305: ...len6d r3 cpos6b r1 qp Deposit I15 4 cpos6d len4d r3 r2 r1 qp Test Bit I16 5 tb x2 ta p2 r3 pos6b y c p1 qp Test NaT I17 5 tb x2 ta p2 r3 x y c p1 qp Nop Hint I18 0 i x3 x6 y imm20a qp Break I19 0 i x3...

Page 306: ...type 0 IP Relative Call B3 5 s d wh imm20b p b1 qp Indirect Branch B4 0 d wh x6 b2 p btype qp Indirect Call B5 1 d wh b2 p b1 qp IP Relative Predict B6 7 s ih t2e imm20b timm7a wh Indirect Predict B7...

Page 307: ...pcode extension ccount5c multimedia shift left complemented shift count immediate count5b count6d multimedia shift right shift right pair shift count immediate cposx deposit complemented bit position...

Page 308: ...0 Reserved if PR qp is 1 B unit instructions medium gray in the gray scale version of the tables cyan in the color version cause an Illegal Operation fault if the predicate register specified by the q...

Page 309: ...in this revision of the architecture future architecture revisions may define these fields as hint extensions These hint extensions will be defined such that the 0 value in each field corresponds to t...

Page 310: ...A2 5 6 shladdp4 A2 7 8 9 sub imm8 A3 A B and imm8 A3 andcm imm8 A3 or imm8 A3 xor imm8 A3 C D E F 40 373635343332 29282726 2019 1312 6 5 0 8 x2a ve x4 x2b r3 r2 r1 qp 4 1 2 1 4 2 7 7 7 6 Instruction O...

Page 311: ...pcodes C E using a 2 bit opcode extension field x2 in bits 35 34 and two 1 bit opcode extension fields in bits 33 ta and 12 c as shown in Table 4 11 40 373635343332 29282726 2019 1312 6 5 0 8 s x2a ve...

Page 312: ...A6 1 cmp4 ne and A6 cmp4 ne or A6 cmp4 ne or andcm A6 1 0 0 cmp4 gt and A7 cmp4 gt or A7 cmp4 gt or andcm A7 1 cmp4 le and A7 cmp4 le or A7 cmp4 le or andcm A7 1 0 cmp4 ge and A7 cmp4 ge or A7 cmp4 ge...

Page 313: ...Opcode Extension x2 tb ta c cmp lt p1 p2 r2 r3 C 0 0 0 0 cmp ltu D cmp eq E cmp lt unc C 1 cmp ltu unc D cmp eq unc E cmp eq and C 1 0 cmp eq or D cmp eq or andcm E cmp ne and C 1 cmp ne or D cmp ne o...

Page 314: ...2 tb ta c cmp gt and p1 p2 r0 r3 C 0 1 0 0 cmp gt or D cmp gt or andcm E cmp le and C 1 cmp le or D cmp le or andcm E cmp ge and C 1 0 cmp ge or D cmp ge or andcm E cmp lt and C 1 cmp lt or D cmp lt o...

Page 315: ...2019 1312 11 6 5 0 C E s x2 ta p2 r3 imm7b c p1 qp 4 1 2 1 6 7 7 1 6 6 Instruction Operands Opcode Extension x2 ta c cmp lt p1 p2 imm8 r3 C 2 0 0 cmp ltu D cmp eq E cmp lt unc C 1 cmp ltu unc D cmp e...

Page 316: ...uu A9 psub1 uus A9 2 pavg1 A9 pavg1 raz A9 3 pavgsub1 A9 4 5 6 7 8 9 pcmp1 eq A9 pcmp1 gt A9 A B C D E F Table 4 14 Multimedia ALU Size 2 4 bit 2 bit Opcode Extensions Opcode Bits 40 37 x2a Bits 35 34...

Page 317: ...Table 4 15 Multimedia ALU Size 4 4 bit 2 bit Opcode Extensions Opcode Bits 40 37 x2a Bits 35 34 za Bit 36 zb Bit 33 x4 Bits 32 29 x2b Bits 28 27 0 1 2 3 8 1 1 0 0 padd4 A9 1 psub4 A9 2 3 4 5 6 7 8 9 p...

Page 318: ...add1 uuu 0 0 2 padd2 uuu 1 padd1 uus 0 0 3 padd2 uus 1 psub1 0 0 1 0 psub2 1 psub4 1 0 psub1 sss 0 0 1 psub2 sss 1 psub1 uuu 0 0 2 psub2 uuu 1 psub1 uus 0 0 3 psub2 uus 1 pavg1 0 0 2 2 pavg2 1 pavg1 r...

Page 319: ...bit field in bits 29 28 x2b and most have a 2 bit field in bits 31 30 x2c as shown in Table 4 17 Table 4 16 Multimedia and Variable Shift 1 bit Opcode Extensions Opcode Bits 40 37 za Bit 36 zb Bit 33...

Page 320: ...d I6 2 0 pack2 uss I2 unpack2 h I2 mix2 r I2 1 pmpy2 r I2 2 pack2 sss I2 unpack2 l I2 mix2 l I2 3 pmin2 I2 pmax2 I2 pmpy2 l I2 3 0 1 pshl2 fixed I8 2 mux2 I4 3 Table 4 19 Multimedia Opcode 7 Size 4 2...

Page 321: ...b Bit 33 ve Bit 32 x2a Bits 35 34 x2b Bits 29 28 x2c Bits 31 30 0 1 2 3 7 1 1 0 0 0 shr u var I5 shl var I7 1 2 shr var I5 3 1 0 1 2 3 2 0 1 2 3 3 0 1 2 3 40 373635343332313029282726 2019 1312 6 5 0 7...

Page 322: ...ix2 l 0 1 mix4 l 1 0 pack2 uss 0 1 0 0 pack2 sss 0 1 2 pack4 sss 1 0 unpack1 h 0 0 0 1 unpack2 h 0 1 unpack4 h 1 0 unpack1 l 0 0 2 unpack2 l 0 1 unpack4 l 1 0 pmin1 u 0 0 1 0 pmax1 u 1 pmin2 0 1 3 0 p...

Page 323: ...82726 201918 141312 6 5 0 7 za x2a zb ve x2c x2b r3 count5b r1 qp 4 1 2 1 1 2 2 1 7 1 5 1 7 6 Instruction Operands Opcode Extension za zb ve x2a x2b x2c pshr2 r1 r3 count5 7 0 1 0 1 3 0 pshr4 1 0 pshr...

Page 324: ...ight Pair I10 40 373635343332313029282726 2019 1312 6 5 0 7 za x2a zb ve x2c x2b r3 0 r1 qp 4 1 2 1 1 2 2 1 7 7 7 6 Instruction Operands Opcode Extension za zb ve x2a x2b x2c popcnt r1 r3 7 0 1 0 1 1...

Page 325: ...7 6 Instruction Operands Opcode Extension x2 x y extr u r1 r3 pos6 len6 5 1 0 0 extr 1 40 373635343332 272625 2019 1312 6 5 0 5 x2 x len6d y cpos6c r2 r1 qp 4 1 2 1 6 1 6 7 7 6 Instruction Operands O...

Page 326: ...nz and I17 tf nz and I30 1 0 0 0 tbit z or I16 1 tnat z or I17 tf z or I30 1 0 tbit nz or I16 1 tnat nz or I17 tf nz or I30 1 0 0 tbit z or andcm I16 1 tnat z or andcm I17 tf z or andcm I30 1 0 tbit...

Page 327: ...nd Table 4 25 summarizes the 6 bit assignments 40 373635343332 2726 201918 141312 11 6 5 0 5 tb x2 ta p2 r3 x y c p1 qp 4 1 2 1 6 7 1 5 1 1 6 6 Instruction Operands Opcode Extension x2 ta tb y x c tna...

Page 328: ...5 33 x6 Bits 30 27 Bits 32 31 0 1 2 3 0 0 0 break i I19 zxt1 I29 mov from ip I25 1 1 bit Ext Table 4 26 zxt2 I29 mov from b I22 2 zxt4 I29 mov i from ar I28 3 mov from pr I25 4 sxt1 I29 5 sxt2 I29 6 s...

Page 329: ...rmal form and a 1 bit hint extension in bit 23 ih see Table 4 56 on page 3 354 4 3 5 1 Move to BR I21 40 373635 3332 272625 6 5 0 0 i x3 x6 imm20a qp 4 1 3 6 1 20 6 Instruction Operands Opcode Extensi...

Page 330: ...management instructions on the M unit See GR AR Moves M Unit on page 3 342 See Miscellaneous I Unit Instructions on page 3 318 for a summary of the I Unit GR AR opcode extensions 40 373635 3332 2726...

Page 331: ...mov i ar3 r2 0 0 2A 40 373635 3332 2726 2019 1312 6 5 0 0 s x3 x6 ar3 imm7b qp 4 1 3 6 7 7 7 6 Instruction Operands Opcode Extension x3 x6 mov i ar3 imm8 0 0 0A 40 373635 3332 2726 2019 1312 6 5 0 0...

Page 332: ...on page 3 324 and Table 4 32 on page 3 325 and the semaphore and get FR opcode extensions in Table 4 33 on page 3 325 The floating point load store 40 373635343332 2726 201918 141312 11 6 5 0 5 tb x2...

Page 333: ...l M2 7 8 ld1 c clr M2 ld2 c clr M2 ld4 c clr M2 ld8 c clr M2 9 ld1 c nc M2 ld2 c nc M2 ld4 c nc M2 ld8 c nc M2 A ld1 c clr acq M2 ld2 c clr acq M2 ld4 c clr acq M2 ld8 c clr acq M2 B C st1 M6 st2 M6 s...

Page 334: ...3 A ld1 c clr acq M3 ld2 c clr acq M3 ld4 c clr acq M3 ld8 c clr acq M3 B C st1 M5 st2 M5 st4 M5 st8 M5 D st1 rel M5 st2 rel M5 st4 rel M5 st8 rel M5 E st8 spill M5 F Table 4 33 Semaphore Get FR 16 By...

Page 335: ...M9 ldfd c nc M9 A B lfetch M18 lfetch excl M18 lfetch fault M18 lfetch fault excl M18 C stfe M13 stf8 M13 stfs M13 stfd M13 D E stf spill M13 F Table 4 35 Floating point Load Lfetch Reg Opcode Extensi...

Page 336: ...8 c nc M8 ldfs c nc M8 ldfd c nc M8 A B lfetch M22 lfetch excl M22 lfetch fault M22 lfetch fault excl M22 C stfe M10 stf8 M10 stfs M10 stfd M10 D E stf spill M10 F Table 4 37 Floating point Load Pair...

Page 337: ...37 m Bit 36 x Bit 27 x6 Bits 35 32 Bits 31 30 0 1 2 3 6 1 1 0 ldfp8 M12 ldfps M12 ldfpd M12 1 ldfp8 s M12 ldfps s M12 ldfpd s M12 2 ldfp8 a M12 ldfps a M12 ldfpd a M12 3 ldfp8 sa M12 ldfps sa M12 ldfp...

Page 338: ...t 09 ld4 a ldhint 0A ld8 a ldhint 0B ld1 sa ldhint 0C ld2 sa ldhint 0D ld4 sa ldhint 0E ld8 sa ldhint 0F ld1 bias ldhint 10 ld2 bias ldhint 11 ld4 bias ldhint 12 ld8 bias ldhint 13 ld1 acq ldhint 14 l...

Page 339: ...s ldhint 07 ld1 a ldhint 08 ld2 a ldhint 09 ld4 a ldhint 0A ld8 a ldhint 0B ld1 sa ldhint 0C ld2 sa ldhint 0D ld4 sa ldhint 0E ld8 sa ldhint 0F ld1 bias ldhint 10 ld2 bias ldhint 11 ld4 bias ldhint 1...

Page 340: ...s ldhint 07 ld1 a ldhint 08 ld2 a ldhint 09 ld4 a ldhint 0A ld8 a ldhint 0B ld1 sa ldhint 0C ld2 sa ldhint 0D ld4 sa ldhint 0E ld8 sa ldhint 0F ld1 bias ldhint 10 ld2 bias ldhint 11 ld4 bias ldhint 12...

Page 341: ...int 31 st4 sthint 32 st8 sthint 33 st1 rel sthint 34 st2 rel sthint 35 st4 rel sthint 36 st8 rel sthint 37 st8 spill sthint 3B st16 sthint r3 r2 ar csd 0 1 30 st16 rel sthint 34 40 373635 3029282726 2...

Page 342: ...3 328 ldfd ldhint 03 ldf8 ldhint 01 ldfe ldhint 00 ldfs s ldhint 06 ldfd s ldhint 07 ldf8 s ldhint 05 ldfe s ldhint 04 ldfs a ldhint 0A ldfd a ldhint 0B ldf8 a ldhint 09 ldfe a ldhint 08 ldfs sa ldhi...

Page 343: ...e 4 39 on page 3 328 ldfd ldhint 03 ldf8 ldhint 01 ldfe ldhint 00 ldfs s ldhint 06 ldfd s ldhint 07 ldf8 s ldhint 05 ldfe s ldhint 04 ldfs a ldhint 0A ldfd a ldhint 0B ldf8 a ldhint 09 ldfe a ldhint 0...

Page 344: ...hint 05 ldfe s ldhint 04 ldfs a ldhint 0A ldfd a ldhint 0B ldf8 a ldhint 09 ldfe a ldhint 08 ldfs sa ldhint 0E ldfd sa ldhint 0F ldf8 sa ldhint 0D ldfe sa ldhint 0C ldf fill ldhint 1B ldfs c clr ldhin...

Page 345: ...fe sthint 30 stf spill sthint 3B 40 373635 3029282726 2019 1312 6 5 0 6 m x6 hint x r3 f2 f1 qp 4 1 6 2 1 7 7 7 6 Instruction Operands Opcode Extension m x x6 hint ldfps ldhint f1 f2 r3 6 0 1 02 See T...

Page 346: ...hint x r3 f2 f1 qp 4 1 6 2 1 7 7 7 6 Instruction Operands Opcode Extension m x x6 hint ldfps ldhint f1 f2 r3 8 6 1 1 02 See Table 4 39 on page 3 328 ldfpd ldhint f1 f2 r3 16 03 ldfp8 ldhint 01 ldfps s...

Page 347: ...9282726 2019 6 5 0 6 m x6 hint x r3 qp 4 1 6 2 1 7 14 6 Instruction Operands Opcode Extension m x x6 hint lfetch excl lfhint r3 6 0 0 2D See Table 4 41 on page 3 337 lfetch fault lfhint 2E lfetch faul...

Page 348: ...Operands Opcode Extension m x x6 hint cmpxchg1 acq ldhint r1 r3 r2 ar ccv 4 0 1 00 See Table 4 39 on page 3 328 cmpxchg2 acq ldhint 01 cmpxchg4 acq ldhint 02 cmpxchg8 acq ldhint 03 cmpxchg1 rel ldhin...

Page 349: ...k M21 40 373635 3029282726 2019 1312 6 5 0 6 m x6 x r2 f1 qp 4 1 6 2 1 7 7 7 6 Instruction Operands Opcode Extension m x x6 setf sig f1 r2 6 0 1 1C setf exp 1D setf s 1E setf d 1F 40 373635 3029282726...

Page 350: ...45 for a summary of the opcode extensions 4 4 6 1 Sync Fence Serialize ALAT Control M24 40 373635 3332 1312 6 5 0 0 s x3 imm20b r1 qp 4 1 3 20 7 6 Instruction Operands Opcode Extension x3 chk a nc r1...

Page 351: ...See System Memory Management on page 3 345 for a summary of the M Unit GR AR opcode extensions 40 373635 33323130 2726 6 5 0 0 x3 x2 x4 0 4 1 3 2 4 21 6 Instruction Opcode Extension x3 x4 x2 flushrs...

Page 352: ...6 ar3 r2 qp 4 1 3 6 7 7 7 6 Instruction Operands Opcode Extension x3 x6 mov m ar3 r2 1 0 2A 40 373635 33323130 2726 2019 1312 6 5 0 0 s x3 x2 x4 ar3 imm7b qp 4 1 3 2 4 7 7 7 6 Instruction Operands Opc...

Page 353: ...ove to PSR M35 4 4 9 3 Move from PSR M36 4 4 9 4 Break M Unit M37 40 373635 33323130 2726 2019 1312 6 5 0 1 x3 sor sol sof r1 qp 4 1 3 2 4 7 7 7 6 Instruction Operands Opcode Extension x3 alloc f r1 a...

Page 354: ...opcode 0 Table 4 44 shows the 3 bit assignments for opcode 1 and Table 4 45 summarizes the 6 bit assignments for opcode 1 Table 4 42 Opcode 0 System Memory Management 3 bit Opcode Extensions Opcode B...

Page 355: ...e rw fault imm2 M40 2 mov to ibr M42 mov from ibr M43 mov m from ar M31 probe r fault imm2 M40 3 mov to pkr M42 mov from pkr M43 probe w fault imm2 M40 4 mov to pmc M42 mov from pmc M43 mov from cr M3...

Page 356: ...373635 3332 2726 2019 15141312 6 5 0 1 x3 x6 r3 i2b qp 4 1 3 6 7 5 2 7 6 Instruction Operands Opcode Extension x3 x6 probe rw fault r3 imm2 1 0 31 probe r fault 32 probe w fault 33 40 373635 3332 272...

Page 357: ...ion x3 x6 mov p r1 rr r3 1 0 10 r1 dbr r3 11 r1 ibr r3 12 r1 pkr r3 13 r1 pmc r3 14 mov r1 pmd r3 15 r1 cpuid r3 17 40 373635 33323130 2726 6 5 0 0 i x3 i2d x4 imm21a qp 4 1 3 2 4 21 6 Instruction Ope...

Page 358: ...dings The branch unit includes branch predict and miscellaneous instructions 40 373635 3332 2726 2019 1312 6 5 0 1 x3 x6 r3 r1 qp 4 1 3 6 7 7 7 6 Instruction Operands Opcode Extension x3 x6 thash r1 r...

Page 359: ...opcode 0 using a 6 bit opcode extension field in bits 32 27 x6 Table 4 48 summarizes these assignments Table 4 47 IP Relative Branch Types Opcode Bits 40 37 btype Bits 8 6 4 0 br cond B1 1 e 2 br wex...

Page 360: ...field p in bit 12 Table 4 51 summarizes these assignments The IP relative and indirect branch instructions all have a 2 bit branch prediction whether opcode hint extension field in bits 34 33 wh as s...

Page 361: ...t Table 4 53 Indirect Call Whether Hint Completer wh Bits 34 32 bwh 0 1 sptk 2 3 spnt 4 5 dptk 6 7 dpnt Table 4 54 Branch Cache Deallocation Hint Completer d Bit 35 dh 0 none 1 clr 40 373635343332 131...

Page 362: ...n page 3 352 See Table 4 54 on page 3 352 br cexit bwh ph dh e t 6 br ctop bwh ph dh e t 7 40 373635343332 1312 11 9 8 6 5 0 5 s d wh imm20b p b1 qp 4 1 1 2 20 1 3 3 6 Instruction Operands Opcode Exte...

Page 363: ...ombination of the loop or exit whether hint completer with the none importance hint completer is undefined The indirect branch predict instructions have a 2 bit branch prediction whether opcode hint e...

Page 364: ...h 0 sptk 1 2 dptk 3 40 373635343332 1312 6 5 4 3 2 0 7 s ih t2e imm20b timm7a wh 4 1 1 2 20 7 1 2 3 Instruction Operands Opcode Extension ih wh brp ipwh ih target25 tag13 7 See Table 4 56 on page 3 35...

Page 365: ...either a second 1 bit extension field in bit 36 q or a 6 bit opcode extension field x6 in bits 32 27 Table 4 59 shows the 1 bit x assignments Table 4 62 shows the additional 1 bit q assignments for th...

Page 366: ...9 fcvt fxu F10 fmix lr F9 A fcvt fx trunc F10 fmix r F9 B fcvt fxu trunc F10 fmix l F9 C fcvt xf F11 fand F9 fsxt r F9 D fandcm F9 fsxt l F9 E for F9 F fxor F9 Table 4 61 Opcode 1 Miscellaneous Float...

Page 367: ...t opcode extension field x in bit 36 The fixed point arithmetic instructions also have a 2 bit opcode extension field x2 in bits 35 34 These assignments are shown in Table 4 65 Table 4 62 Reciprocal A...

Page 368: ...le 4 63 on page 3 358 The parallel floating point compare instructions are described on page 3 362 40 3736353433 2726 2019 1312 6 5 0 8 D x sf f4 f3 f2 f1 qp 4 1 2 7 7 7 7 6 Instruction Operands Opcod...

Page 369: ...cmp unord F4 fcmp unord unc F4 Table 4 67 Floating point Class 1 bit Opcode Extensions Opcode Bits 40 37 ta Bit 12 5 0 fclass m F5 1 fclass m unc F5 40 373635343332 2726 2019 1312 11 6 5 0 4 rb sf ra...

Page 370: ...iprocal Square Root Approximation instructions The first in major op 0 encodes the full register variant The second in major op 1 encodes the parallel variant F7 40 373635343332 2726 2019 1312 6 5 0 0...

Page 371: ...he parallel compare instructions are all encoded in major op 1 F8 40 373635343332 2726 2019 1312 6 5 0 0 1 sf x x6 f3 f2 f1 qp 4 1 2 1 6 7 7 7 6 Instruction Operands Opcode Extension x x6 sf fmin sf f...

Page 372: ...rge se 12 fmix lr 39 fmix r 3A fmix l 3B fsxt r 3C fsxt l 3D fpack 28 fswap 34 fswap nl 35 fswap nr 36 fand 2C fandcm 2D for 2E fxor 2F fpmerge s 1 10 fpmerge ns 11 fpmerge se 12 40 373635343332 2726...

Page 373: ...Extension x x6 fcvt xf f1 f2 0 0 1C 40 373635343332 2726 2019 1312 6 5 0 0 sf x x6 omask7c amask7b qp 4 1 2 1 6 7 7 7 6 Instruction Operands Opcode Extension x x6 sf fsetc sf amask7 omask7 0 0 04 See...

Page 374: ...tion slot For brl the imm39 field and a 2 bit Ignored field occupy the L instruction slot 4 7 1 Miscellaneous X Unit Instructions The miscellaneous X unit instructions are encoded in major opcode 0 us...

Page 375: ...ted by an I unit Table 4 69 Misc X Unit 3 bit Opcode Extensions Opcode Bits 40 37 x3 Bits 35 33 0 0 6 bit Ext Table 4 70 1 2 3 4 5 6 7 Table 4 70 Misc X Unit 6 bit Opcode Extensions Opcode Bits 40 37...

Page 376: ...351 Table 4 52 on page 3 352 and Table 4 54 on page 3 352 4 7 3 1 Long Branch X3 Table 4 71 Move Long 1 bit Opcode Extensions Opcode Bits 40 37 vc Bit 20 6 0 movl X2 1 40 373635 2726 22212019 1312 6 5...

Page 377: ...uction encoding 40 373635343332 1312 11 9 8 6 5 0 40 2 1 0 D i d wh imm20b p b1 qp imm39 4 1 1 2 20 1 3 3 6 39 2 Instruction Operands Opcode Extension p wh d brl call bwh ph dh e l b1 target64 D See T...

Page 378: ...sign_ext s 8 i 7 imm7b 9 M5 M10 imm9 sign_ext s 8 i 7 imm7a 9 M17 inc3 sign_ext s 1 1 i2b 3 1 1 4 i2b 6 I20 M20 M21 target25 IP sign_ext s 20 imm13c 7 imm7a 21 4 M22 M23 target25 IP sign_ext s 20 imm2...

Page 379: ...3 370 Volume 3 Instruction Formats a This encoding causes an Illegal Operation fault if the value of the qualifying predicate is 1...

Page 380: ...ded as an immediate in the instruction Since the PSR bits to be written can be determined by examining the encoded instruction the instruction is treated as only writing those bits which have a corres...

Page 381: ...some cases other than CRs where pairs of instructions explicitly encode the same resource serialization is implied There are cases where it is architecturally allowed to omit a serialization and that...

Page 382: ...ed resources are represented in a single row of a table using the notation as a substitute for the number of the resource In such cases the semantics of the table are as if each numbered resource had...

Page 383: ...register base registers in CFM and always write AR EC the rotating register bases in CFM and PR 63 even if they do not change their values or if their PR qp is false Instructions of type mod sched br...

Page 384: ...C mod sched brs br ret mov to AR EC br call brl call br ia mod sched brs mov from AR EC impliedF AR EFLAG mov to AR EFLAG br ia mov from AR EFLAG impliedF AR FCR mov to AR FCR br ia mov from AR FCR im...

Page 385: ...iedF AR SSD mov to AR SSD br ia mov from AR SSD impliedF AR UNAT in 0 63 mov to AR UNAT st8 spill br ia ld8 fill mov from AR UNAT impliedF AR in 8 15 20 22 23 31 33 35 37 39 41 43 46 47 67 111 none br...

Page 386: ...from CR IVR mov from CR IRR1 data CR ISR mov to CR ISR mov from CR ISR data CR ITIR mov to CR ITIR mov from CR ITIR data itc i itc d itr i itr d implied CR ITM mov to CR ITM mov from CR ITM data CR I...

Page 387: ...n access data ptc g ptc ga ptc l ptr d itr d impliedF ptr d mem readers mem writers non access data ptc g ptc ga ptc l ptr d none itr d itc d impliedF FR in 0 1 none fr readers1 none FR in 2 127 fr wr...

Page 388: ...nomovpr1 mov from PR12 mov to PR12 none PR in 1 15 pr writers1 mov to PR allreg7 pr readers nobr nomovpr1 mov from PR mov to PR12 impliedF pr writers fp1 pr readers br1 impliedF pr writers int1 mov to...

Page 389: ...R mov from PSR um impliedF PSR bn bsw rfi gr readers10 gr writers10 impliedF PSR cpl epc br ret priv ops br call brl call epc mov from AR ITC mov from AR RUC mov to AR ITC mov to AR RSC mov to AR RUC...

Page 390: ...mov from PSR impliedF PSR ia rfi all none PSR ic sys mask writers partial7 mov to PSR l mov from PSR impliedF cover itc i itc d itr i itr d mov from interruption CR mov to interruption CR data rfi mov...

Page 391: ...from IND PMD mov from PSR mov to PSR um rum sum impliedF PSR ss rfi all impliedF PSR tb mov to PSR l branches chk fchkf data mov from PSR impliedF rfi branches chk fchkf mov from PSR impliedF PSR up...

Page 392: ...shrs mov to AR BSPSTORE impliedF AR CCV mov to AR CCV impliedF AR CFLG mov to AR CFLG impliedF AR CSD ld16 mov to AR CSD impliedF AR EC br ret mod sched brs mov to AR EC impliedF AR EFLAG mov to AR EF...

Page 393: ...call1 brl call1 none CFM mod sched brs br call brl call br ret alloc clrrrb cover rfi impliedF CPUID none none CR CMCV mov to CR CMCV impliedF CR DCR mov to CR DCR impliedF CR EOI mov to CR EOI SC Sec...

Page 394: ...mpliedF DTR itr d impliedF itr d ptr d impliedF ptr d none FR in 0 1 none none FR in 2 127 fr writers1 ldf c1 ldfp c1 impliedF GR0 none none GR in 1 127 ld c1 gr writers1 impliedF IBR mov to IND IBR3...

Page 395: ...ers fp1 pr unc writers int1 pr norm writers fp1 pr norm writers int1 pr or writers1 mov to PR allreg7 mov to PR rotreg impliedF PSR ac user mask writers partial7 mov to PSR um sys mask writers partial...

Page 396: ...nstruction or encoded as its PR qp PSR mfh fr writers9 none user mask writers partial7 mov to PSR um fr writers9 sys mask writers partial7 mov to PSR l rfi user mask writers partial7 mov to PSR um sys...

Page 397: ...e PSR bn bit is only accessed when one of GR16 31 is specified in the instruction Rule 11 The target predicates are written independently of PR qp but source registers are only read if PR qp is true R...

Page 398: ...pcmp Field sf s0 fpcmp s1 fpcmp Field sf s1 fpcmp s2 fpcmp Field sf s2 fpcmp s3 fpcmp Field sf s3 fr readers fp arith fp non arith mem writers fp pr writers fp chk s Format in M21 getf fr writers fp a...

Page 399: ...fp8 sa lfetch all lfetch lfetch fault lfetch Field lftype fault lfetch nofault lfetch Field lftype lfetch postinc lfetch Format in M20 M22 mem readers mem readers fp mem readers int mem readers alat l...

Page 400: ...from CR Field cr3 CMCV mov from CR DCR mov from CR Field cr3 DCR mov from CR EOI mov from CR Field cr3 EOI mov from CR IFA mov from CR Field cr3 IFA mov from CR IFS mov from CR Field cr3 IFS mov from...

Page 401: ...mov to AR CFLG mov to AR M Field ar3 CFLG mov to AR CSD mov to AR M Field ar3 CSD mov to AR EC mov to AR I Field ar3 EC mov to AR EFLAG mov to AR M Field ar3 EFLAG mov to AR FCR mov to AR M Field ar3...

Page 402: ...Field cr3 in LRR0 LRR1 mov to CR PMV mov to CR Field cr3 PMV mov to CR PTA mov to CR Field cr3 PTA mov to CR TPR mov to CR Field cr3 TPR mov to IND mov_indirect Format in M42 mov to IND CPUID mov to...

Page 403: ...om IND mov ip mov to PSR l mov to PSR um mov from PSR mov from PSR um movl mux nop f nop i nop m nop x or pack padd pavg pavgsub pcmp pmax pmin pmpy pmpyshr popcnt probe all psad pshl pshladd pshr psh...

Page 404: ...ov to AR BSPSTORE rfi st st1 st2 st4 st8 st8 spill st16 st postinc stf Format in M10 st Format in M5 stf stfs stfd stfe stf8 stf spill sxt sxt1 sxt2 sxt4 sys mask writers partial rsm ssm unpack unpack...

Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...

Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...

Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...

Page 408: ...Fault 2 151 brl Instruction 3 30 brp Instruction 3 32 BSF Instruction 4 35 BSP RSE Backing Store Pointer Register 1 29 BSPSTORE RSE Backing Store Pointer for Memory Stores Register 1 30 BSR Instructio...

Page 409: ...R Instruction 4 94 EOI End of External Interrupt Register 2 124 epc Instruction 2 555 3 53 Epilog Count Register EC 1 33 Explicit Prefetch 1 70 External Controller Interrupts 2 96 External Interrupt 2...

Page 410: ...struction 3 93 FNSAVE Instruction 4 162 FNSTCW Instruction 4 176 FNSTENV Instruction 4 178 FNSTSW Instruction 4 180 for Instruction 3 94 fpabs Instruction 3 95 fpack Instruction 3 96 fpamax Instructio...

Page 411: ...re Trap 2 232 IA 32 Interruption 2 111 IA 32 Interruption Vector Definitions 2 213 IA 32 Interruption Vector Descriptions 2 213 IA 32 Memory Ordering 2 265 IA 32 Physical Memory References 2 262 IA 32...

Page 412: ...ruptions 2 95 2 537 Interrupts 2 96 2 114 External Interrupt Architecture 2 603 Interval Time Counter ITC 1 31 Interval Timer Match Register ITM 2 32 Interval Timer Offset ITO 2 34 Interval Timer Vect...

Page 413: ...2 615 MINPS Instruction 4 523 MINSS Instruction 4 525 mix Instruction 3 169 MMX technology 1 20 MOV Instruction 4 284 mov Instruction 3 172 MOVAPS Instruction 4 527 MOVD Instruction 4 401 MOVHLPS Ins...

Page 414: ...3 PAL_BRAND_INFO 2 366 PAL_BUS_GET_FEATURES 2 367 PAL_BUS_SET_FEATURES 2 369 PAL_CACHE_FLUSH 2 370 PAL_CACHE_INFO 2 374 PAL_CACHE_INIT 2 376 PAL_CACHE_LINE_INIT 2 377 PAL_CACHE_PROT_INFO 2 378 PAL_CAC...

Page 415: ...INSW Instruction 4 569 PMINUB Instruction 4 570 PMOVMSKB Instruction 4 571 pmpy Instruction 3 213 pmpyshr Instruction 3 214 PMULHUW Instruction 4 572 PMULHW Instruction 4 431 PMULLW Instruction 4 433...

Page 416: ...n 4 337 REPNZ Instruction 4 337 REPZ Instruction 4 337 Reserved Variables 2 351 Reset Event 2 95 2 351 Resource Utilization Counter RUC 1 31 2 33 RET Instruction 4 340 rfi Instruction 2 543 3 236 RID...

Page 417: ...on Cache 2 49 2 567 Template Field Encoding 1 38 Templates 1 141 TEST Instruction 4 381 tf Instruction 3 263 thash Instruction 3 265 TLB Translation Lookaside Buffer 2 47 2 565 tnat Instruction 3 266...

Page 418: ...te Dependency 1 149 WRMSR Instruction 4 389 X XADD Instruction 4 391 XCHG Instruction 4 393 xchg Instruction 2 508 3 274 XLAT Instruction 4 395 XLATB Instruction 4 395 xma Instruction 3 276 xmpy Instr...

Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...

Page 420: ......

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