3:12
Volume 3: Instruction Reference
(64-bits not including the NaT bit) where the notation
GR[addr]
is used. The syntactical
differences between the code found in the Operation section and ANSI C is listed in
The Operation section contains code that specifies only the execution semantics of each
instruction and does not include any behavior relating to instruction fetch (e.g.,
interrupts and faults caused during fetch). The Interruptions section does not list any
faults that may be caused by instruction fetch or by mandatory RSE loads. The code to
raise certain pervasive faults and actions is not included in the code in the Operation
section. These faults and actions are listed in
. The Single step trap applies to
all instructions and is not listed in the Interruptions section.
Table 2-3.
Register File Notation
Register File
C Notation
Assembly
Mnemonic
Indirect
Access
Application registers
AR
ar
Branch registers
BR
b
Control registers
CR
cr
CPU identification registers
CPUID
cpuid
Y
Data breakpoint registers
DBR
dbr
Y
Instruction breakpoint registers
IBR
ibr
Y
Data TLB translation cache
DTC
N/A
Data TLB translation registers
DTR
dtr
Y
Floating-point registers
FR
f
General registers
GR
r
Instruction TLB translation cache
ITC
N/A
Instruction TLB translation registers
ITR
itr
Y
Protection key registers
PKR
pkr
Y
Performance monitor configuration registers
PMC
pmc
Y
Performance monitor data registers
PMD
pmd
Y
Predicate registers
PR
p
Region registers
RR
rr
Y
Table 2-4.
C Syntax Differences
Syntax
Function
{msb:lsb}, {bit}
Bit field specifier. When appended to a variable, denotes a bit field extending from the
most significant bit specified by “msb” to the least significant bit specified by “lsb”
including bits “msb” and “lsb.” If “msb” and “lsb” are equal then a single bit is
accessed. The second form denotes a single bit.
u>, u>=, u<, u<=
Unsigned inequality relations. Variables on either side of the operator are treated as
unsigned.
u>>, u>>=
Unsigned right shift. Zeroes are shifted into the most significant bit position.
u+
Unsigned addition. Operands are treated as unsigned, and zero-extended.
u*
Unsigned multiplication. Operands are treated as unsigned.
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......