Intel Itanium 9150M, Manual, Page: 121 / 420

3:112 Volume 3: Instruction Reference
fpmerge
Operation: if (PR[ qp ]) {
fp_check_target_register( f
1
);
if (tmp_isrcode = fp_reg_disabled( f
1
, f
2
, f
3
, 0))
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[ f
2
]) || fp_is_natval(FR[ f
3
])) {
FR[ f
1
] = NATVAL;
} else {
if (neg_sign_form) {
tmp_res_hi = (!FR[ f
2
].significand{63} << 31)
| (FR[ f
3
].significand{62:32});
tmp_res_lo = (!FR[ f
2
].significand{31} << 31)
| (FR[ f
3
].significand{30:0});
} else if (sign_form) {
tmp_res_hi = (FR[ f
2
].significand{63} << 31)
| (FR[ f
3
].significand{62:32});
tmp_res_lo = (FR[ f
2
].significand{31} << 31)
| (FR[ f
3
].significand{30:0});
} else { // sign_exp_form
tmp_res_hi = (FR[ f
2
].significand{63:55} << 23)
| (FR[ f
3
].significand{54:32});
tmp_res_lo = (FR[ f
2
].significand{31:23} << 23)
| (FR[ f
3
].significand{22:0});
}
FR[ f
1
].significand = fp_concatenate(tmp_res_hi, tmp_res_lo);
FR[ f
1
].exponent = FP_INTEGER_EXP;
FR[ f
1
].sign = FP_SIGN_POSITIVE;
}
fp_update_psr( f
1
);
}
FP Exceptions:
None
Interruptions:
Illegal Operation fault Disabled Floating-point Register fault
Figure 2-17. Floating-point Parallel Merge Sign and Exponent Operation
81 0 80 64 63
FR
f
2
FR
f
3
FR
f
1
0
1003E
32 31 23 22 55 54
81 0 80 64 63 32 31 23 22 55 54
81 0 80 64 63 32 31 23 22 55 54