Intel Itanium 9150M, Manual

Page: 194 / 420

Volume 3: Instruction Reference 3:185
mov psr
mov — Move Processor Status Register
Format: (
qp
) mov
r
1
= psr from_form M36
(
qp
) mov psr.l =
r
2
to_form M35
Description:
The source operand is copied to the destination register. See Section 3.3.2, “Processor
Status Register (PSR)” on page 2:23 .
For move from processor status register, PSR bits {36:35} and {31:0} are read, and
copied into GR
r
1
. All other bits of the PSR read as zero.
For move to processor status register, GR
r
2
is read, bits {31:0} copied into PSR{31:0}
and bits {63:32} are ignored. Bits {31:0} of GR
r
2
corresponding to reserved fields of
the PSR must be 0 or a Reserved Register/Field fault will result. An implementation may
also raise Reserved Register/Field fault if bits {63:32} in GR
r
2
corresponding to
reserved fields of the PSR are non-zero.
Moves to and from the PSR can only be performed at the most privileged level, and
when PSR.vm is 0.
The contents of the interruption resources (that are overwritten when the PSR.ic bit is
1) are undefined if an interruption occurs between the enabling of the PSR.ic bit and a
subsequent instruction serialize operation.
Operation: if (PR[ qp ]) {
if (from_form)
check_target_register( r
1
);
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (from_form) {
if (PSR.vm == 1)
virtualization_fault();
tmp_val = zero_ext(PSR{31:0}, 32); // read lower 32 bits
tmp_val |= PSR{36:35} << 35; // read mc and it bits
GR[ r
1
] = tmp_val; // other bits read as zero
GR[ r
1
].nat = 0;
} else { // to_form
if (GR[ r
2
].nat)
register_nat_consumption_fault(0);
if (is_reserved_field(PSR_TYPE, PSR_MOVPART, GR[ r
2
]))
reserved_register_field_fault();
if (PSR.vm == 1)
virtualization_fault();
PSR{31:0} = GR[ r
2
]{31:0};
}
}
Interruptions:
Illegal Operation fault Reserved Register/Field fault
Privileged Operation fault Virtualization fault
Register NaT Consumption fault
Serialization:
Software must issue an instruction or data serialize operation before issuing
instructions dependent upon the altered PSR bits. Unlike with the
rsm
instruction, the
PSR.i bit is not treated specially when cleared.