Intel Itanium 9150M, Manual

Page: 158 / 420

Volume 3: Instruction Reference 3:149
itr
itr — Insert Translation Register
Format: (
qp
) itr.i itr[
r
3
] =
r
2
instruction_form M42
(
qp
) itr.d dtr[
r
3
] =
r
2
data_form M42
Description:
A translation is inserted into the instruction or data translation register specified by the
contents of GR
r
3
. GR
r
2
specifies the physical address portion of the translation. ITIR
specifies the protection key, page size and additional information. The virtual address is
specified by the IFA register and the region register is selected by IFA{63:61}.
As described in Table 4-1, “Purge Behavior of TLB Inserts and Purges” on page 2:52 ,
the TLB is first purged of any entries that overlap with the newly inserted translation.
The translation previously contained in the TR slot specified by GR
r
3
is not necessarily
purged from the processor's TLBs and may remain as a TC entry. To ensure that the
previous TR translation is purged, software must use explicit
ptr
instructions before
inserting the new TR entry.
This instruction can only be executed at the most privileged level, and when PSR.ic and
PSR.vm are both 0.
Operation: if (PR[ qp ]) {
if (PSR.ic)
illegal_operation_fault();
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (GR[ r
3
].nat || GR[ r
2
].nat)
register_nat_consumption_fault(0);
slot = GR[ r
3
]{7:0};
tmp_size = CR[ITIR].ps;
tmp_va = CR[IFA]{60:0};
tmp_rid = RR[CR[IFA]{63:61}].rid;
tmp_va = align_to_size_boundary(tmp_va, tmp_size);
tmp_tr_type = instruction_form ? ITR_TYPE : DTR_TYPE;
if (is_reserved_reg(tmp_tr_type, slot))
reserved_register_field_fault();
if (is_reserved_field(TLB_TYPE, GR[ r
2
], CR[ITIR]))
reserved_register_field_fault();
if (!impl_check_mov_ifa() &&
unimplemented_virtual_address(CR[IFA], PSR.vm))
unimplemented_data_address_fault(0);
if (PSR.vm == 1)
virtualization_fault();
if (instruction_form) {
tlb_must_purge_itc_entries(tmp_rid, tmp_va, tmp_size);
tlb_may_purge_dtc_entries(tmp_rid, tmp_va, tmp_size);
tlb_insert_inst(slot, GR[
r
2
], CR[ITIR], CR[IFA], tmp_rid, TR);
} else { // data_form
tlb_must_purge_dtc_entries(tmp_rid, tmp_va, tmp_size);
tlb_may_purge_itc_entries(tmp_rid, tmp_va, tmp_size);
tlb_insert_data(slot, GR[
r
2
], CR[ITIR], CR[IFA], tmp_rid, TR);
}
}