Intel Itanium 9150M, Manual

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3:358 Volume 3: Instruction Formats
Most floating-point instructions have a 2-bit opcode extension field in bits 35:34 (sf)
which encodes the FPSR status field to be used.
Table 4-63 summarizes these
assignments.
4.6.1 Arithmetic
The floating-point arithmetic instructions are encoded within major opcodes 8 – D using
a 1-bit opcode extension field (x) in bit 36 and a 2-bit opcode extension field (sf) in bits
35:34. The opcode and x assignments are shown in
Table 4-64 .
The fixed-point arithmetic and parallel floating-point select instructions are encoded
within major opcode E using a 1-bit opcode extension field (x) in bit 36. The fixed-point
arithmetic instructions also have a 2-bit opcode extension field (x
2
) in bits 35:34. These
assignments are shown in Table 4-65 .
Table 4-62. Reciprocal Approximation 1-bit Opcode Extensions
Opcode
Bits 40:37
x
Bit 33
q
Bit 36
0
1
0 frcpa F6
1 frsqrta F7
1
0 fprcpa F6
1 fprsqrta F7
Table 4-63. Floating-point Status Field Completer
sf
Bits 35:34
sf
0 .s0
1 .s1
2 .s2
3 .s3
Table 4-64. Floating-point Arithmetic 1-bit Opcode Extensions
x
Bit 36
Opcode
Bits 40:37
8 9 A B C D
0 fma F1 fma.d F1 fms F1 fms.d F1 fnma F1 fnma.d F1
1 fma.s F1 fpma F1 fms.s F1 fpms F1 fnma.s F1 fpnma F1
Table 4-65. Fixed-point Multiply Add and Select Opcode Extensions
Opcode
Bits 40:37
x
Bit 36
x
2
Bits 35:34
0 1 2 3
E
0 fselect F3
1 xma.l F2 xma.hu F2 xma.h F2