3:344
Volume 3: Instruction Formats
4.4.9
Miscellaneous M-Unit Instructions
The miscellaneous M-unit instructions are encoded in major opcode 0 along with the
system/memory management instructions. See
for a summary of the opcode extensions.
4.4.9.1
Allocate Register Stack Frame
Note:
The three immediates in the instruction encoding are formed from the operands
as follows:
sof =
i
+
l
+
o
sol =
i
+
l
sor =
r
>> 3
4.4.9.2
Move to PSR
4.4.9.3
Move from PSR
4.4.9.4
Break (M-Unit)
40
37 36 35
33 32 31 30
27 26
20 19
13 12
6 5
0
x
3
sor
sol
sof
r
1
qp
4
1
3
2
4
7
7
7
6
Instruction
Operands
Opcode
Extension
x
3
alloc
r
1
= ar.pfs,
i
,
l
,
o
,
r
6
40
37 36 35
33 32
27 26
20 19
13 12
6 5
0
x
3
x
6
r
2
qp
4
1
3
6
7
7
7
6
Instruction
Operands
Opcode
Extension
x
3
x
6
mov
psr.l =
r
2
0
2D
mov
psr.um =
r
2
29
40
37 36 35
33 32
27 26
13 12
6 5
0
x
3
x
6
r
1
qp
4
1
3
6
14
7
6
Instruction
Operands
Opcode
Extension
x
3
x
6
mov
r
1
= psr
0
25
mov
r
1
= psr.um
21
40
37 36 35
33 32 31 30
27 26 25
6 5
0
i
x
3
x
2
x
4
imm
20a
qp
4
1
3
2
4
1
20
6
Instruction
Operands
Opcode
Extension
x
3
x
4
x
2
break.m
imm
21
0
0
0
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......
