Intel Itanium 9150M, Manual

Page: 263 / 420

3:254 Volume 3: Instruction Reference
stf
stf — Floating-point Store
Format: (
qp
) stf
fsz
.
sthint
[
r
3
] =
f
2
normal_form, no_base_update_form M13
(
qp
) stf
fsz
.
sthint
[
r
3
] =
f
2
,
imm
9
normal_form, imm_base_update_form M10
(
qp
) stf8.
sthint
[
r
3
] =
f
2
integer_form, no_base_update_form M13
(
qp
) stf8.
sthint
[
r
3
] =
f
2
,
imm
9
integer_form, imm_base_update_form M10
(
qp
) stf.spill.
sthint
[
r
3
] =
f
2
spill_form, no_base_update_form M13
(
qp
) stf.spill.
sthint
[
r
3
] =
f
2
,
imm
9
spill_form, imm_base_update_form M10
Description:
A value, consisting of fsz bytes, is generated from the value in FR
f
2
and written to
memory starting at the address specified by the value in GR
r
3
. In the normal_form, the
value in FR
f
2
is converted to the memory format and then stored. In the integer_form,
the significand of FR
f
2
is stored. The values of the
fsz
completer are given in Table 2-35
on page 3:157 . In the normal_form or the integer_form, if the NaT bit corresponding to
GR
r
3
is 1 or if FR
f
2
contains NaTVal, a Register NaT Consumption fault is taken. See
Section 5.1, “Data Types and Formats” on page 1:85 for details on conversion from
floating-point register format.
In the spill_form, a 16-byte value from FR
f
2
is stored without conversion. This
instruction is used for spilling a register. See Section 4.4.4, “Control Speculation” on
page 1:60 for details.
In the imm_base_update form, the value in GR
r
3
is added to a signed immediate value
(
imm
9
) and the result is placed back in GR
r
3
. This base register update is done after the
store, and does not affect the store address.
The ALAT is queried using the physical memory address and the access size, and all
overlapping entries are invalidated.
The value of the
sthint
completer specifies the locality of the memory access. The values
of the
sthint
completer are given in Table 2-51 on page 3:252 . A prefetch hint is implied
in the base update forms. The address specified by the value in GR
r
3
after the base
update acts as a hint to prefetch the indicated cache line. This prefetch uses the locality
hints specified by
sthint
. See Section 4.4.6, “Memory Hierarchy Control and
Consistency” on page 1:69 .
Hardware support for
stfe
(10-byte) instructions that reference a page that is neither a
cacheable page with write-back policy nor a NaTPage is optional. On processor models
that do not support such
stfe
accesses, an Unsupported Data Reference fault is raised
when an unsupported reference is attempted.