Intel Itanium 9150M, Manual

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3:374 Volume 3: Resource and Dependency Semantics
5.3.1 Special Case Instruction Rules
The following rules apply to the specified instructions when they appear in Table 5-2 ,
Table 5-3 , Table 5-4 , or Table 5-5 :
• An instruction always reads a given resource if its qualifying predicate is 1 and it
appears in the “Reader” column of the table (except as noted). An instruction
always writes a given resource if its qualifying predicate is 1 and it appears in the
“Writer” column of the table (except as noted). An instruction never reads or writes
the specified resource if its qualifying predicate is 0 (except as noted). These rules
include branches and their qualifying predicate. Instructions in the
unpredicatable-instructions class have no qualifying predicate and thus always
read or write their resources (except as noted).
• An instruction of type mov-from-PR reads all PRs if its PR[qp] is true. If the
PR[qp] is false, then only the PR[qp] is read.
• An instruction of type mov-to-PR writes only those PRs as indicated by the
immediate mask encoded in the instruction.
• A
st8.spill
only writes AR[UNAT]{ X } where X equals the value in bits 8:3 of the
store’s data address. A
ld8.fill
instruction only reads AR[UNAT]{ Y } where Y
equals the value in bits 8:3 of the load’s data address.
• Instructions of type mod-sched-brs always read AR[EC] and the rotating register
base registers in CFM, and always write AR[EC], the rotating register bases in CFM,
and PR[63] even if they do not change their values or if their PR[qp] is false.
• Instructions of type mod-sched-brs-counted always read and write AR[LC], even
if they do not change its value.
• For instructions of type pr-or-writers or pr-and-writers , if their completer is
or.andcm
, then only the first target predicate is an or-compare and the second
target predicate is an and-compare. Similarly, if their completer is
and.orcm
, then
only the second target predicate is an or-compare and the first target predicate is
an and-compare.
•
rum
and
sum
only read PSR.sp when the bit corresponding to PSR.up (bit 2) is set in
the immediate field of the instruction.
5.3.2 RAW Dependency Table
Table 5-2 architecturally defines the following information:
impliedF Instruction Group Break (same as above). An undefined value is returned, or an Illegal
Operation fault may be taken. If no fault is taken,
the value returned is unpredictable, and may be
unrelated to past writes, but will not be data which
could not be accessed by the current process (e.g.,
if PSR.cpl != 0, the undefined value to return
cannot be read from some control register).
stop Stop. Writer and reader must be separated by a stop.
none None N/A
specific Implementation Specific
SC Special Case Described elsewhere in book, see referenced
section in the entry.
Table 5-1. Semantics of Dependency Codes (Continued)
Semantics of
Dependency Code
Serialization Type Required Effects of Serialization Violation