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Volume 3: Resource and Dependency Semantics
3:387
5.3.4
WAR Dependency Table
A general rule specific to the WAR table:
1. WAR dependencies are always allowed within instruction groups except for the
entry in
below. The readers and subsequent writers specified must be
separated by a stop in order to have defined behavior.
5.3.5
Listing of Rules Referenced in Dependency Tables
The following rules restrict the specific instances in which some of the instructions in
the tables cause a dependency and must be applied where referenced to correctly
interpret those entries. Rules only apply to the instance of the instruction class, or
instruction mnemonic prefix where the rule is referenced as a superscript. If the rule is
referenced in
where instruction classes are defined, then it applies to all
instances of the instruction class.
Rule 1. These instructions only write a register when that register’s number is explicitly
encoded as a target of the instruction and is only read when it is encoded as a
source of the instruction (or encoded as its PR[qp]).
PSR.mfh
none
,
,
, rfi
impliedF
PSR.mfl
none
,
,
, rfi
impliedF
PSR.pk
,
impliedF
PSR.pp
,
impliedF
PSR.ri
rfi
impliedF
PSR.rt
, rfi
impliedF
PSR.si
,
impliedF
PSR.sp
,
impliedF
PSR.ss
rfi
impliedF
PSR.tb
, rfi
impliedF
PSR.up
,
,
impliedF
PSR.vm
rfi, vmsw
impliedF
RR#
impliedF
RSE
impliedF
Table 5-4.
WAR Dependencies Organized by Resource
Resource Name
Readers
Writers
Semantics of Dependency
PR63
stop
Table 5-3.
WAW Dependencies Organized by Resource (Continued)
Resource Name
Writers
Semantics of
Dependency
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
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