Intel Itanium 9150M, Manual, Page: 30 / 420

Volume 3: Instruction Reference 3:21
br
the branch condition is simply the value of the specified predicate register. These basic
branch types are:
• cond: If the qualifying predicate is 1, the branch is taken. Otherwise it is not taken.
• call: If the qualifying predicate is 1, the branch is taken and several other actions
occur:
• The current values of the Current Frame Marker (CFM), the EC application
register and the current privilege level are saved in the Previous Function State
application register.
• The caller’s stack frame is effectively saved and the callee is provided with a
frame containing only the caller’s output region.
• The rotation rename base registers in the CFM are reset to 0.
• A return link value is placed in BR
b
1
.
• return: If the qualifying predicate is 1, the branch is taken and the following
occurs:
• CFM, EC, and the current privilege level are restored from PFS. (The privilege
level is restored only if this does not increase privilege.)
• The caller’s stack frame is restored.
• If the return lowers the privilege, and PSR.lp is 1, then a Lower-Privilege
Transfer trap is taken.
• ia: The branch is taken unconditionally, if it is not intercepted by the OS. The effect
of the branch is to invoke the IA-32 instruction set (by setting PSR.is to 1) and
begin processing IA-32 instructions at the virtual linear target address contained in
BR
b
2
{31:0}. If the qualifying predicate is not PR 0, an Illegal Operation fault is
raised. If instruction set transitions are disabled (PSR.di is 1), then a Disabled
Instruction Set Transition fault is raised.
The IA-32 target effective address is calculated relative to the current code
segment, i.e. EIP{31:0} = BR
b
2
{31:0} - CSD.base. The IA-32 instruction set can
be entered at any privilege level, provided PSR.di is 0. If PSR.dfh is 1, a Disabled FP
Register fault is raised on the target IA-32 instruction. No register bank switch nor
change in privilege level occurs during the instruction set transition.
Software must ensure the code segment descriptor (CSD) and selector (CS) are
loaded before issuing the branch. If the target EIP value exceeds the code segment
limit or has a code segment privilege violation, an IA_32_Exception(GPFault) is
raised on the target IA-32 instruction. For entry into 16-bit IA-32 code, if BR
b
2
is
not within 64K-bytes of CSD.base a GPFault is raised on the target instruction.
EFLAG.rf is unmodified until the successful completion of the first IA-32 instruction.
PSR.da, PSR.id, PSR.ia, PSR.dd, and PSR.ed are cleared to zero after
br.ia
completes execution and before the first IA-32 instruction begins execution.
EFLAG.rf is not cleared until the target IA-32 instruction successfully completes.
Software must set PSR properly before branching to the IA-32 instruction set;
otherwise processor operation is undefined. See
Table 3-2, “Processor Status
Register Fields” on page 2:24 for details.
Software must issue a
mf
instruction before the branch if memory ordering is
required between IA-32 processor consistent and Itanium unordered memory
references. The processor does not ensure Itanium-instruction-set-generated
writes into the instruction stream are seen by subsequent IA-32 instruction fetches.
br.ia
does not perform an instruction serialization operation. The processor does
ensure that prior writes (even in the same instruction group) to GRs and FRs are
observed by the first IA-32 instruction. Writes to ARs within the same instruction