Intel Itanium 9150M, Manual

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Volume 3: Instruction Reference 3:39
cmp
cmp — Compare
Format: (
qp
) cmp.
crel
.
ctype p
1
,
p
2
=
r
2
,
r
3
register_form A6
(
qp
) cmp.
crel
.
ctype p
1
,
p
2
=
imm
8
,
r
3
imm8_form A8
(
qp
) cmp.
crel
.
ctype p
1
,
p
2
= r0,
r
3
parallel_inequality_form A7
(
qp
) cmp.
crel
.
ctype p
1
,
p
2
=
r
3
, r0 pseudo-op
Description:
The two source operands are compared for one of ten relations specified by
crel
. This
produces a boolean result which is 1 if the comparison condition is true, and 0
otherwise. This result is written to the two predicate register destinations,
p
1
and
p
2
.
The way the result is written to the destinations is determined by the compare type
specified by
ctype
.
The compare types describe how the predicate targets are updated based on the result
of the comparison. The normal type simply writes the compare result to one target, and
the complement to the other. The parallel types update the targets only for a particular
comparison result. This allows multiple simultaneous OR-type or multiple simultaneous
AND-type compares to target the same predicate register.
The unc type is special in that it first initializes both predicate targets to 0, independent
of the qualifying predicate . It then operates the same as the normal type. The behavior
of the compare types is described in Table 2-15 . A blank entry indicates the predicate
target is left unchanged.
In the register_form the first operand is GR
r
2
; in the imm8_form the first operand is
taken from the sign-extended
imm
8
encoding field; and in the parallel_inequality_form
the first operand must be GR 0. The parallel_inequality_form is only used when the
compare type is one of the parallel types, and the relation is an inequality (>, >=, <,
<=). See below.
If the two predicate register destinations are the same (
p
1
and
p
2
specify the same
predicate register), the instruction will take an Illegal Operation fault, if the qualifying
predicate is 1, or if the compare type is unc.
Of the ten relations, not all are directly implemented in hardware. Some are actually
pseudo-ops. For these, the assembler simply switches the source operand specifiers
and/or switches the predicate target specifiers and uses an implemented relation. For
some of the pseudo-op compares in the imm8_form, the assembler subtracts 1 from
the immediate value, making the allowed immediate range slightly different. Of the six
parallel compare types, three of the types are actually pseudo-ops. The assembler
Table 2-15. Comparison Types
ctype
Pseudo-op
of
PR[ qp ]==0
PR[ qp ]==1
Result==0,
No Source NaTs
Result==1,
No Source NaTs
One or More
Source NaTs
PR[ p
1
] PR[ p
2
] PR[ p
1
] PR[ p
2
] PR[ p
1
] PR[ p
2
] PR[ p
1
] PR[ p
2
]
none 0 1 1 0 0 0
unc 0 0 0 1 1 0 0 0
or 1 1
and 0 0 0 0
or.andcm 1 0
orcm or 1 1
andcm and 0 0 0 0
and.orcm or.andcm 0 1