Intel Itanium 9150M, Manual

Page: 261 / 420

3:252 Volume 3: Instruction Reference
st
For the sixteen_byte_form, Illegal Operation fault is raised on processor models that do
not support the instruction. CPUID register 4 indicates the presence of the feature on
the processor model. See
Section 3.1.11, “Processor Identification Registers” on
page 1:34 for details.
Operation:
if (PR[ qp ]) {
size = spill_form ? 8 : (sixteen_byte_form ? 16 : sz) ;
itype = WRITE;
if (size == 16) itype |= UNCACHE_OPT;
otype = (
sttype == ‘rel’) ? RELEASE : UNORDERED;
if (sixteen_byte_form && !instruction_implemented(ST16))
illegal_operation_fault();
if (imm_base_update_form)
check_target_register( r
3
);
if (GR[ r
3
].nat || ((sixteen_byte_form || normal_form) && GR[ r
2
].nat))
register_nat_consumption_fault(WRITE);
paddr = tlb_translate(GR[ r
3
], size, itype, PSR.cpl, &mattr,
&tmp_unused);
if (spill_form && GR[ r
2
].nat) {
natd_gr_write(GR[ r
2
], paddr, size, UM.be, mattr, otype, sthint );
}
else {
if (sixteen_byte_form)
mem_write16(GR[ r
2
], AR[CSD], paddr, UM.be, mattr, otype, sthint);
else
mem_write(GR[ r
2
], paddr, size, UM.be, mattr, otype, sthint );
}
if (spill_form) {
bit_pos = GR[ r
3
]{8:3};
AR[UNAT]{bit_pos} = GR[ r
2
].nat;
}
alat_inval_multiple_entries(paddr, size);
if (imm_base_update_form) {
GR[ r
3
] = GR[ r
3
] + sign_ext( imm
9
, 9);
GR[ r
3
].nat = 0;
mem_implicit_prefetch(GR[ r
3
], sthint , WRITE);
}
}
Interruptions:
Illegal Operation fault Data Key Miss fault
Register NaT Consumption fault Data Key Permission fault
Unimplemented Data Address fault Data Access Rights fault
Data Nested TLB fault Data Dirty Bit fault
Alternate Data TLB fault Data Access Bit fault
VHPT Data fault Data Debug fault
Table 2-51. Store Hints
sthint Completer Interpretation
none Temporal locality, level 1
nta Non-temporal locality, all levels