Intel Itanium 9150M, Manual

Page: 259 / 420

3:250 Volume 3: Instruction Reference
ssm
ssm — Set System Mask
Format: (
qp
) ssm
imm
24
M44
Description:
The
imm
24
operand is ORed with the system mask (PSR{23:0}) and the result is placed
in the system mask. See Section 3.3.2, “Processor Status Register (PSR)” on
page 2:23 .
The PSR system mask can only be written at the most privileged level, and when
PSR.vm is 0.
The contents of the interruption resources (that are overwritten when the PSR.ic bit is
1), are undefined if an interruption occurs between the enabling of the PSR.ic bit and a
subsequent instruction serialize operation.
Operation:
if (PR[ qp ]) {
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (is_reserved_field(PSR_TYPE, PSR_SM, imm
24
))
reserved_register_field_fault();
if (PSR.vm == 1)
virtualization_fault();
if ( imm
24
{1}) PSR{1} = 1;) // be
if ( imm
24
{2}) PSR{2} = 1;) // up
if ( imm
24
{3}) PSR{3} = 1;) // ac
if ( imm
24
{4}) PSR{4} = 1;) // mfl
if ( imm
24
{5}) PSR{5} = 1;) // mfh
if ( imm
24
{13}) PSR{13} = 1;) // ic
if ( imm
24
{14}) PSR{14} = 1;) // i
if ( imm
24
{15}) PSR{15} = 1;) // pk
if ( imm
24
{17}) PSR{17} = 1;) // dt
if ( imm
24
{18}) PSR{18} = 1;) // dfl
if ( imm
24
{19}) PSR{19} = 1;) // dfh
if ( imm
24
{20}) PSR{20} = 1;) // sp
if ( imm
24
{21}) PSR{21} = 1;) // pp
if ( imm
24
{22}) PSR{22} = 1;) // di
if ( imm
24
{23}) PSR{23} = 1;) // si
}
Interruptions:
Privileged Operation fault Virtualization fault
Reserved Register/Field fault
Serialization:
Software must issue a data serialize or instruction serialize operation before issuing
instructions dependent upon the altered PSR bits from the
ssm
instruction. Unlike with
the
rsm
instruction, setting the PSR.i bit is not treated specially. Refer to Section 3.2,
“Serialization” on page 2:17 for a description of serialization.