Intel Itanium 9150M, Manual

Page: 55 / 420

3:46 Volume 3: Instruction Reference
cmpxchg
cmpxchg — Compare and Exchange
Format: (
qp
) cmpxchg
sz
.
sem
.
ldhint r
1
= [
r
3
],
r
2
, ar.ccv M16
(
qp
) cmp8xchg16.
sem
.
ldhint r
1
= [
r
3
],
r
2
, ar.csd, ar.ccv sixteen_byte_form M16
Description:
A value consisting of
sz
bytes (8 bytes for
cmp8xchg16
) is read from memory starting at
the address specified by the value in GR
r
3
. The value is zero extended and compared
with the contents of the
cmpxchg
Compare Value application register (AR[CCV]). If the
two are equal, then the least significant sz bytes of the value in GR r
2
are written to
memory starting at the address specified by the value in GR r
3
. For
cmp8xchg16
, if the
two are equal, then 8-bytes from GR r
2
are stored at the specified address ignoring bit
3 (GR
r
3
& ~0x8), and 8 bytes from the Compare and Store Data application register
(AR[CSD]) are stored at that a 8 ((GR
r
3
& ~0x8) + 8). The zero-extended
value read from memory is placed in GR r
1
and the NaT bit corresponding to GR r
1
is
cleared.
The values of the
sz
completer are given in Table 2-19 . The
sem
completer specifies the
type of semaphore operation. These operations are described in Table 2-20 . See
Section 4.4.7, “Sequentiality Attribute and Ordering” on page 2:82 for details on
memory ordering.
If the address specified by the value in GR
r
3
is not naturally aligned to the size of the
value being accessed in memory, an Unaligned Data Reference fault is taken
independent of the state of the User Mask alignment checking bit, UM.ac (PSR.ac in the
Processor Status Register). For the
cmp8xchg16
instruction, the address specified must
be 8-byte aligned.
The memory read and write are guaranteed to be atomic. For the
cmp8xchg16
instruction, the 8-byte memory read and the 16-byte memory write are guaranteed to
be atomic.
Both read and write access privileges for the referenced page are required. The write
access privilege check is performed whether or not the memory write is performed.
This instruction is only supported to cacheable pages with write-back write policy.
Accesses to NaTPages cause a Data NaT Page Consumption fault. Accesses to pages
with other memory attributes cause an Unsupported Data Reference fault.
The value of the
ldhint
completer specifies the locality of the memory access. The values
of the
ldhint
completer are given in Table 2-34 on page 3:152 . Locality hints do not
Table 2-19. Memory Compare and Exchange Size
sz Completer Bytes Accessed
1 1
2 2
4 4
8 8
Table 2-20. Compare and Exchange Semaphore Types
sem
Completer
Ordering
Semantics
Semaphore Operation
acq Acquire The memory read/write is made visible prior to all subsequent data memory
accesses.
rel Release The memory read/write is made visible after all previous data memory
accesses.