Intel Itanium 9150M, Manual

Page: 70 / 420

Volume 3: Instruction Reference 3:61
fc
fc — Flush Cache
Format: (
qp
) fc
r
3
invalidate_line_form M28
(
qp
) fc.i
r
3
instruction_cache_coherent_form M28
Description:
In the invalidate_line form, the cache line associated with the address specified by the
value of GR
r
3
is invalidated from all levels of the processor cache hierarchy. The
invalidation is broadcast throughout the coherence domain. If, at any level of the cache
hierarchy, the line is inconsistent with memory it is written to memory before
invalidation. The line size affected is at least 32-bytes (aligned on a 32-byte boundary).
An implementation may flush a larger region.
In the instruction_cache_coherent form, the cache line specified by GR r
3
is flushed in
an implementation-specific manner that ensures that the instruction caches are
coherent with the data caches. The
fc.i
instruction is not required to invalidate the
targeted cache line nor write the targeted cache line back to memory if it is inconsistent
with memory, but may do so if this is required to make the instruction caches coherent
with the data caches. The
fc.i
instruction is broadcast throughout the coherence
domain if necessary to make all instruction caches coherent. The line size affected is at
least 32-bytes (aligned on a 32-byte boundary). An implementation may flush a larger
region.
When executed at privilege level 0,
fc
and
fc.i
perform no access rights or protection
key checks. At other privilege levels,
fc
and
fc.i
perform access rights checks as if
they were 1-byte reads, but do not perform any protection key checks (regardless of
PSR.pk).
The memory attribute of the page containing the affected line has no effect on the
behavior of these instructions. The
fc
instruction can be used to remove a range of
addresses from the cache by first changing the memory attribute to non-cacheable and
then flushing the range.
These instructions follow data dependency ordering rules; they are ordered only with
respect to previous load, store or semaphore instructions to the same line.
fc
and
fc.i
have data dependencies in the sense that any prior stores by this processor will be
included in the flush operation. Subsequent memory operations to the same line need
not wait for prior
fc
or
fc.i
completion before being globally visible.
fc
and
fc.i
are
unordered operations, and are not affected by a memory fence (
mf
) instruction. These
instructions are ordered with respect to the
sync.i
instruction.
Operation: if (PR[ qp ]) {
itype = NON_ACCESS|FC|READ;
if (GR[
r
3
].nat)
register_nat_consumption_fault(itype);
tmp_paddr = tlb_translate_nonaccess(GR[ r
3
], itype);
if (invalidate_line_form)
mem_flush(tmp_paddr);
else // instruction_cache_coherent_form
make_icache_coherent(tmp_paddr);
}