Intel Itanium 9150M, Manual

Page: 163 / 420

3:154 Volume 3: Instruction Reference
ld
Operation: if (PR[ qp ]) {
size = fill_form ? 8 : (sixteen_byte_form ? 16 : sz) ;
speculative = ( ldtype == ‘s’ || ldtype == ‘sa’);
advanced = ( ldtype == ‘a’ || ldtype == ‘sa’);
check_clear = ( ldtype == ‘c.clr’ || ldtype == ‘c.clr.acq’);
check_no_clear = ( ldtype == ‘c.nc’);
check = check_clear || check_no_clear;
acquire = (acquire_form ||
ldtype == ‘acq’ || ldtype == ‘c.clr.acq’);
otype = acquire ? ACQUIRE : UNORDERED;
bias = (
ldtype == ‘bias’) ? BIAS : 0 ;
translate_address = 1;
read_memory = 1;
itype = READ;
if (speculative) itype |= SPEC ;
if (advanced) itype |= ADVANCE ;
if (size == 16) itype |= UNCACHE_OPT ;
if (sixteen_byte_form && !instruction_implemented(LD16))
illegal_operation_fault();
if ((reg_base_update_form || imm_base_update_form) && ( r
1
== r
3
))
illegal_operation_fault();
check_target_register( r
1
);
if (reg_base_update_form || imm_base_update_form)
check_target_register( r
3
);
if (reg_base_update_form) {
tmp_r2 = GR[ r
2
];
tmp_r2nat = GR[ r
2
].nat;
}
if (!speculative && GR[ r
3
].nat) // fault on NaT address
register_nat_consumption_fault(itype);
defer = speculative && (GR[ r
3
].nat || PSR.ed);// defer exception if spec
if (check && alat_cmp(GENERAL, r
1
)) {
translate_address = alat_translate_address_on_hit( ldtype , GENERAL,
r
1
);
read_memory = alat_read_memory_on_hit( ldtype , GENERAL, r
1
);
}
if (!translate_address) {
if (check_clear || advanced) // remove any old alat entry
alat_inval_single_entry(GENERAL, r
1
);
} else {
if (!defer) {
paddr = tlb_translate(GR[ r
3
], size, itype, PSR.cpl, &mattr,
&defer);
spontaneous_deferral(paddr, size, UM.be, mattr, otype,
bias | ldhint , &defer);
if (!defer && read_memory) {
if (size == 16) {
mem_read_pair(&val, &val_ar, paddr, size, UM.be, mattr,
otype, ldhint );
}
else {