Intel Itanium 9150M, Manual

Page: 81 / 420

3:72 Volume 3: Instruction Reference
fcvt.xf
fcvt.xf — Convert Signed Integer to Floating-point
Format: (
qp
) fcvt.xf
f
1
=
f
2
F11
Description:
The 64-bit significand of FR
f
2
is treated as a signed integer and its register file precision
floating-point representation is placed in FR
f
1
.
If FR
f
2
is a NaTVal, FR
f
1
is set to NaTVal instead of the computed result.
This operation is always exact and is unaffected by the rounding mode.
Operation:
if (PR[ qp ]) {
fp_check_target_register( f
1
);
if (tmp_isrcode = fp_reg_disabled( f
1
, f
2
, 0, 0))
disabled_fp_register_fault(tmp_isrcode, 0);
if (fp_is_natval(FR[ f
2
])) {
FR[ f
1
] = NATVAL;
} else {
tmp_res = FR[ f
2
];
if (tmp_res.significand{63}) {
tmp_res.significand = (~tmp_res.significand) + 1;
tmp_res.sign = 1;
} else
tmp_res.sign = 0;
tmp_res.exponent = FP_INTEGER_EXP;
tmp_res = fp_normalize(tmp_res);
FR[ f
1
].significand = tmp_res.significand;
FR[ f
1
].exponent = tmp_res.exponent;
FR[ f
1
].sign = tmp_res.sign;
}
fp_update_psr(
f
1
);
}
FP Exceptions:
None
Interruptions:
Illegal Operation fault Disabled Floating-point Register fault