Volume 3: Instruction Reference
3:275
xchg
Operation:
if (PR[
qp
]) {
check_target_register(
r
1
);
if (GR[
r
3
].nat || GR[
r
2
].nat)
register_nat_consumption_fault(SEMAPHORE);
paddr = tlb_translate(GR[
r
3
],
sz
, SEMAPHORE, PSR.cpl, &mattr,
&tmp_unused);
if (!ma_supports_semaphores(mattr))
unsupported_data_reference_fault(SEMAPHORE, GR[
r
3
]);
val = mem_xchg(GR[
r
2
], paddr,
sz
, UM.be, mattr, ACQUIRE,
ldhint
);
alat_inval_multiple_entries(paddr,
sz
);
GR[
r
1
] = zero_ext(val,
sz
* 8);
GR[
r
1
].nat = 0;
}
Interruptions:
Illegal Operation fault
Data Key Miss fault
Register NaT Consumption fault
Data Key Permission fault
Unimplemented Data Address fault
Data Access Rights fault
Data Nested TLB fault
Data Dirty Bit fault
Alternate Data TLB fault
Data Access Bit fault
VHPT Data fault
Data Debug fault
Data TLB fault
Unaligned Data Reference fault
Data Page Not Present fault
Unsupported Data Reference fault
Data NaT Page Consumption fault
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......