3:342
Volume 3: Instruction Formats
4.4.6.2
RSE Control
4.4.6.3
Integer ALAT Entry Invalidate
4.4.6.4
Floating-point ALAT Entry Invalidate
4.4.6.5
Flush Cache
4.4.7
GR/AR Moves (M-Unit)
The M-Unit GR/AR move instructions are encoded in major opcode 0 along with the
system/memory management instructions. (Some ARs are accessed using system
control instructions on the I-unit. See
“GR/AR Moves (I-Unit)” on page 3:321
.) See
“System/Memory Management” on page 3:345
for a summary of the M-Unit GR/AR
opcode extensions.
40
37 36 35
33 32 31 30
27 26
6 5
0
x
3
x
2
x
4
0
4
1
3
2
4
21
6
Instruction
Opcode
Extension
x
3
x
4
x
2
flushrs
0
C
0
loadrs
A
37 36 35
33 32 31 30
27 26
13 12
6 5
0
x
3
x
2
x
4
r
1
qp
4
1
3
2
4
14
7
6
Instruction
Operands
Opcode
Extension
x
3
x
4
x
2
invala.e
r
1
0
2
1
40
37 36 35
33 32 31 30
27 26
13 12
6 5
0
x
3
x
2
x
4
f
1
qp
4
1
3
2
4
14
7
6
Instruction
Operands
Opcode
Extension
x
3
x
4
x
2
invala.e
f
1
0
3
1
40
37 36 35
33 32
27 26
20 19
6 5
0
x
x
3
x
6
r
3
qp
4
1
3
6
7
14
6
Instruction
Operands
Opcode
Extension
x
3
x
6
x
fc
r
3
0
30
0
fc.i
1
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......
