Volume 3: Instruction Formats
3:359
4.6.1.1
Floating-point Multiply Add
4.6.1.2
Fixed-point Multiply Add
4.6.2
Parallel Floating-point Select
4.6.3
Compare and Classify
The predicate setting floating-point compare instructions are encoded within major
opcode 4 using three 1-bit opcode extension fields in bits 33 (r
a
), 36 (r
b
), and 12 (t
a
),
and a 2-bit opcode extension field (sf) in bits 35:34. The opcode, r
a
, r
b
, and t
a
. The sf assignments are shown in
.
The parallel floating-point compare instructions are described on
40
37 36 35 34 33
27 26
20 19
13 12
6 5
0
x sf
f
4
f
3
f
2
f
1
qp
4
1
2
7
7
7
7
6
Instruction
Operands
Opcode
Extension
x
sf
fma.
sf
f
1
=
f
3
,
f
4
,
f
2
0
fma.s.
sf
1
fma.d.
sf
0
fpma.
sf
1
fms.
sf
0
fms.s.
sf
1
fms.d.
sf
0
fpms.
sf
1
fnma.
sf
0
fnma.s.
sf
1
fnma.d.
sf
0
fpnma.
sf
1
40
37 36 35 34 33
27 26
20 19
13 12
6 5
0
x x
2
f
4
f
3
f
2
f
1
qp
4
1
2
7
7
7
7
6
Instruction
Operands
Opcode
Extension
x
x
2
xma.l
f
1
=
f
3
,
f
4
,
f
2
1
0
xma.h
3
xma.hu
2
40
37 36 35 34 33
27 26
20 19
13 12
6 5
0
x
f
4
f
3
f
2
f
1
qp
4
1
2
7
7
7
7
6
Instruction
Operands
Opcode
Extension
x
fselect
f
1
=
f
3
,
f
4
,
f
2
0
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......
