Intel Itanium 9150M, Manual

Page: 171 / 420

3:162 Volume 3: Instruction Reference
ldfp
Operation: if (PR[ qp ]) {
size = single_form ? 8 : 16;
speculative = ( fldtype == ‘s’ || fldtype == ‘sa’);
advanced = ( fldtype == ‘a’ || fldtype == ‘sa’);
check_clear = ( fldtype == ‘c.clr’);
check_no_clear = ( fldtype == ‘c.nc’);
check = check_clear || check_no_clear;
translate_address = 1;
read_memory = 1;
itype = READ;
if (speculative) itype |= SPEC;
if (advanced) itype |= ADVANCE;
if (fp_reg_bank_conflict(f1, f2))
illegal_operation_fault();
if (base_update_form)
check_target_register( r
3
);
fp_check_target_register( f
1
);
fp_check_target_register( f
2
);
if (tmp_isrcode = fp_reg_disabled( f
1
, f
2
, 0, 0))
disabled_fp_register_fault(tmp_isrcode, itype);
if (!speculative && GR[ r
3
].nat) // fault on NaT address
register_nat_consumption_fault(itype);
defer = speculative && (GR[ r
3
].nat || PSR.ed);// defer exception if spec
if (check && alat_cmp(FLOAT, f
1
)) {
translate_address = alat_translate_address_on_hit( fldtype , FLOAT, f
1
);
read_memory = alat_read_memory_on_hit( fldtype , FLOAT, f
1
);
}
if (!translate_address) {
if (check_clear || advanced) // remove any old ALAT entry
alat_inval_single_entry(FLOAT, f
1
);
} else {
if (!defer) {
paddr = tlb_translate(GR[ r
3
], size, itype, PSR.cpl, &mattr,
&defer);
spontaneous_deferral(paddr, size, UM.be, mattr, UNORDERED,
ldhint , &defer);
if (!defer && read_memory)
mem_read_pair(&f1_val, &f2_val, paddr, size, UM.be,
mattr, UNORDERED, ldhint );
}
if (check_clear || advanced)
// remove any old ALAT entry
alat_inval_single_entry(FLOAT, f
1
);
if (speculative && defer) {
FR[ f
1
] = NATVAL;
FR[ f
2
] = NATVAL;
} else if (advanced && !speculative && defer) {
FR[ f
1
] = (integer_form ? FP_INT_ZERO : FP_ZERO);