Intel Itanium 9150M, Manual, Page: 272 / 420

Volume 3: Instruction Reference 3:263
tf
tf — Test Feature
Format: (
qp
) tf.
trel
.
ctype p
1
,
p
2
=
imm
5
I30
Description:
The
imm
5
value (in the range of 32-63) selects the feature bit defined in Table 2-57 to be
tested from the features vector in CPUID[4]. See Section 3.1.11, “Processor
Identification Registers” on page 1:34 for details on CPUID registers. The selected bit
forms a single-bit result either complemented or not depending on the
trel
completer.
This result is written to the two predicate register destinations
p
1
and
p
2
. The way the
result is written to the destinations is determined by the compare type specified by
ctype
. See the Compare instruction and Table 2-15 on page 3:39 .
The
trel
completer values .nz and .z indicate non-zero and zero sense of the test. For
normal and unc types, only the .z value is directly implemented in hardware; the .nz
value is actually a pseudo-op. For it, the assembler simply switches the predicate
target specifiers and uses the implemented relation. For the parallel types, both
relations are implemented in hardware.
If the two predicate register destinations are the same (
p
1
and
p
2
specify the same
predicate register), the instruction will take an Illegal Operation fault, if the qualifying
predicate is set or the compare type is unc.
Table 2-55. Test Feature Relations for Normal and unc tf
trel Test Relation Pseudo-op of
nz selected feature available z p
1

p
2
z selected feature unavailable
Table 2-56. Test Feature Relations for Parallel tf
trel Test Relation
nz selected feature available
z selected feature unavailable
Table 2-57. Test Feature Features Assignment
imm
5
Feature Symbol Feature
32 @clz
clz
feature
33 @mpy
mpy4
,
mpyshl4
feature
34 - 63 none Not currently defined