Intel Itanium 9150M, Manual, Page: 161 / 420

3:152 Volume 3: Instruction Reference
ld
For more details on ordered, biased, speculative, advanced and check loads see
Section 4.4.4, “Control Speculation” on page 1:60 and Section 4.4.5, “Data
Speculation” on page 1:63 . For more details on ordered loads see Section 4.4.7,
“Memory Access Ordering” on page 1:73 . See Section 4.4.6, “Memory Hierarchy
Control and Consistency” on page 1:69 for details on biased loads. Details on memory
attributes are described in Section 4.4, “Memory Attributes” on page 2:75 .
For the non-speculative load types, if NaT bit associated with GR
r
3
is 1, a Register NaT
Consumption fault is taken. For speculative and speculative advanced loads, no fault is
raised, and the exception is deferred. For the base-update calculation, if the NaT bit
associated with GR
r
2
is 1, the NaT bit associated with GR
r
3
is set to 1 and no fault is
raised.
The value of the
ldhint
completer specifies the locality of the memory access. The values
of the
ldhint
completer are given in Table 2-34 . A prefetch hint is implied in the base
update forms. The address specified by the value in GR
r
3
after the base update acts as
a hint to prefetch the indicated cache line. This prefetch uses the locality hints specified
by
ldhint . Prefetch and locality hints do not affect program functionality and may be
ignored by the implementation. See Section 4.4.6, “Memory Hierarchy Control and
Consistency” on page 1:69 for details.
sa Speculative
Advanced load
An entry is added to the ALAT, and certain exceptions may be deferred.
Deferral causes the target register’s NaT bit to be set, and the
processor ensures that no ALAT entry exists for the target register. The
absence of an ALAT entry is later used to detect deferral or collision.
c.nc Check load
– no clear
The ALAT is searched for a matching entry. If found, no load is done
and the target register is unchanged. Regardless of ALAT hit or miss,
base register updates are performed, if specified. An implementation
may optionally cause the ALAT lookup to fail independent of whether an
ALAT entry matches. If not found, a load is performed, and an entry is
added to the ALAT (unless the referenced data page has a
non-speculative attribute, in which case no ALAT entry is allocated).
c.clr Check load
– clear
The ALAT is searched for a matching entry. If found, the entry is
removed, no load is done and the target register is unchanged.
Regardless of ALAT hit or miss, base register updates are performed, if
specified. An implementation may optionally cause the ALAT lookup to
fail independent of whether an ALAT entry matches. If not found, a clear
check load behaves like a normal load.
c.clr.acq Ordered check load
– clear
This type behaves the same as the unordered clear form, except that
the ALAT lookup (and resulting load, if no ALAT entry is found) is
performed with acquire semantics.
acq Ordered load An ordered load is performed with acquire semantics.
bias Biased load A hint is provided to the implementation to acquire exclusive ownership
of the accessed cache line.
Table 2-34. Load Hints
ldhint Completer Interpretation
none Temporal locality, level 1
Table 2-33. Load Types (Continued)
ldtype
Completer
Interpretation Special Load Operation