3:20
Volume 3: Instruction Reference
br
br — Branch
Format:
(
qp
) br.
btype
.
bwh
.
ph
.
dh target
25
ip_relative_form
(
qp
) br.
btype
.
bwh
.
ph
.
dh b
1
=
target
25
call_form, ip_relative_form
br.
btype
.
bwh
.
ph
.
dh target
25
counted_form, ip_relative_form
br.
ph
.
dh target
25
pseudo-op
(
qp
) br.
btype
.
bwh
.
ph
.
dh b
2
indirect_form
(
qp
) br.
btype
.
bwh
.
ph
.
dh b
1
=
b
2
call_form, indirect_form
br.
ph
.
dh b
2
pseudo-op
Description:
A branch condition is evaluated, and either a branch is taken, or execution continues
with the next sequential instruction. The execution of a branch logically follows the
execution of all previous non-branch instructions in the same instruction group. On a
taken branch, execution begins at slot 0.
Branches can be either IP-relative, or indirect. For IP-relative branches, the
target
25
operand, in assembly, specifies a label to branch to. This is encoded in the branch
instruction as a signed immediate displacement (
imm
21
) between the target bundle and
the bundle containing this instruction (
imm
21
=
target
25
- IP >> 4). For indirect branches,
the target address is taken from BR
b
2
.
There are two pseudo-ops for unconditional branches. These are encoded like a
conditional branch (
btype
= cond), with the
qp
field specifying PR 0, and with the
bwh
hint of sptk.
The branch type determines how the branch condition is calculated and whether the
branch has other effects (such as writing a link register). For the basic branch types,
Table 2-6.
Branch Types
btype
Function
Branch Condition
Target Address
cond or
none
Conditional branch
Qualifying predicate
IP-rel or Indirect
call
Conditional procedure call
Qualifying predicate
IP-rel or Indirect
ret
Conditional procedure return
Qualifying predicate
Indirect
ia
Invoke IA-32 instruction set
Unconditional
Indirect
cloop
Counted loop branch
Loop count
IP-rel
ctop, cexit
Mod-scheduled counted loop
Loop count and epilog
count
IP-rel
wtop, wexit
Mod-scheduled while loop
Qualifying predicate and
epilog count
IP-rel
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......