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Volume 3: Instruction Reference
3:43
cmp4
cmp4 — Compare 4 Bytes
Format:
(
qp
) cmp4.
crel
.
ctype p
1
,
p
2
=
r
2
,
r
3
register_form
(
qp
) cmp4.
crel
.
ctype p
1
,
p
2
=
imm
8
,
r
3
imm8_form
(
qp
) cmp4.
crel
.
ctype p
1
,
p
2
= r0,
r
3
parallel_inequality_form
(
qp
) cmp4.
crel
.
ctype p
1
,
p
2
=
r
3
, r0
pseudo-op
Description:
The least significant 32 bits from each of two source operands are compared for one of
ten relations specified by
crel
. This produces a boolean result which is 1 if the
comparison condition is true, and 0 otherwise. This result is written to the two predicate
register destinations,
p
1
and
p
2
. The way the result is written to the destinations is
determined by the compare type specified by
ctype
. See the Compare instruction and
.
In the register_form the first operand is GR
r
2
; in the imm8_form the first operand is
taken from the sign-extended
imm
8
encoding field; and in the parallel_inequality_form
the first operand must be GR 0. The parallel_inequality_form is only used when the
compare type is one of the parallel types, and the relation is an inequality (>, >=, <,
<=). See the Compare instruction and
If the two predicate register destinations are the same (
p
1
and
p
2
specify the same
predicate register), the instruction will take an Illegal Operation fault, if the qualifying
predicate is 1, or if the compare type is unc.
Of the ten relations, not all are directly implemented in hardware. Some are actually
pseudo-ops. See the Compare instruction and
and
The range for immediates is given below.
Table 2-18.
Immediate Range for 32-bit Compares
crel
Compare Relation
(
a
rel
b
)
Immediate Range
eq
a
==
b
-128 .. 127
ne
a
!=
b
-128 .. 127
lt
a
<
b
signed
-128 .. 127
le
a
<=
b
-127 .. 128
gt
a
>
b
-127 .. 128
ge
a
>=
b
-128 .. 127
ltu
a
<
b
unsigned
0 .. 127, 2
32
-128 .. 2
32
-1
leu
a
<=
b
1 .. 128, 2
32
-127 .. 2
32
gtu
a
>
b
1 .. 128, 2
32
-127 .. 2
32
geu
a
>=
b
0 .. 127, 2
32
-128 .. 2
32
-1
Summary of Contents for Itanium 9150M
Page 1: ......
Page 209: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault...
Page 405: ...3 396 Volume 3 Resource and Dependency Semantics...
Page 406: ...3 397 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index...
Page 407: ...3 398 Intel Itanium Architecture Software Developer s Manual Rev 2 3...
Page 419: ...INDEX Index 12 Index for Volumes 1 2 3 and 4...
Page 420: ......