IDT 89HPES24N3A, User Manual

Page: 98 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 4 April 10, 2008
Notes
0x038 DWord P0_EROMBASE EROMBASE - Expansion ROM Base Address Register (0x038)
on page 9-19
0x03C Byte P0_INTRLINE INTRLINE - Interrupt Line Register (0x03C) on page 9-19
0x03D Byte P0_INTRPIN INTRPIN - Interrupt PIN Register (0x03D) on page 9-19
0x03E Word P0_BCTRL BCTRL - Bridge Control Register (0x03E) on page 9-20
0x040 DWord P0_PCIECAP PCIECAP - PCI Express Capability (0x040) on page 9-21
0x044 DWord P0_PCIEDCAP PCIEDCAP - PCI Express Device Capabilities (0x044) on page 9-
21
0x048 Word P0_PCIEDCTL PCIEDCTL - PCI Express Device Control (0x048) on page 9-22
0x04A Word P0_PCIEDSTS PCIEDSTS - PCI Express Device Status (0x04A) on page 9-23
0x04C DWord P0_PCIELCAP PCIELCAP - PCI Express Link Capabilities (0x04C) on page 9-24
0x050 Word P0_PCIELCTL PCIELCTL - PCI Express Link Control (0x050) on page 9-25
0x052 Word P0_PCIELSTS PCIELSTS - PCI Express Link Status (0x052) on page 9-26
0x064 DWord P0_PCIEDCAP2 PCIEDCAP2 - PCI Express Device Capabilities 2 (0x064) on
page 9-31
0x068 Word P0_PCIEDCTL2 PCIEDCTL2 - PCI Express Device Control 2 (0x068) on page 9-
31
0x06A Word P0_PCIEDSTS2 PCIEDSTS2 - PCI Express Device Status 2 (0x06A) on page 9-
31
0x06C DWord P0_PCIELCAP2 PCIELCAP2 - PCI Express Link Capabilities 2 (0x06C) on page
9-31
0x070 Word P0_PCIELCTL2 PCIELCTL2 - PCI Express Link Control 2 (0x070) on page 9-32
0x072 Word P0_PCIELSTS2 PCIELSTS2 - PCI Express Link Status 2 (0x072) on page 9-32
0x0C0 DWord P0_PMCAP PMCAP - PCI Power Management Capabilities (0x0C0) on page
9-33
0x0C4 DWord P0_PMCSR PMCSR - PCI Power Management Control and Status (0x0C4) on
page 9-34
0x0F8 Word P0_ECFGADDR ECFGADDR - Extended Configuration Space Access Address
(0x0F8) on page 9-36
0x0FC Word P0_ECFGDATA ECFGDATA - Extended Configuration Space Access Data
(0x0FC) on page 9-37
0x100 Dword P0_AERCAP AERCAP - AER Capabilities (0x100) on page 9-37
0x104 Dword P0_AERUES AERUES - AER Uncorrectable Error Status (0x104) on page 9-37
0x108 Dword P0_AERUEM AERUEM - AER Uncorrectable Error Mask (0x108) on page 9-38
0x10C Dword P0_AERUESV AERUESV - AER Uncorrectable Error Severity (0x10C) on page
9-39
0x110 Dword P0_AERCES AERCES - AER Correctable Error Status (0x110) on page 9-41
0x114 Dword P0_AERCEM AERCEM - AER Correctable Error Mask (0x114) on page 9-41
0x118 Dword P0_AERCTL AERCTL - AER Control (0x118) on page 9-42
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 2 of 5)