IDT 89HPES24N3A, User Manual

Page: 135 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 41 April 10, 2008
Notes
AERCES - AER Correctable Error Status (0x110)
AERCEM - AER Correctable Error Mask (0x114)
Bit
Field
Field
Name
Type
Default
Value
Description
0 RCVERR RW1C 0x0
Sticky
Receiver Error Status. This bit is set when the physical
layer detects a receiver error.
5:1 Reserved RO 0x0 Reserved field.
6 BADTLP RW1C 0x0
Sticky
Bad TLP Status. This bit is set when a bad TLP is detected.
7 BADDLLP RW1C 0x0
Sticky
Bad DLLP Status. This bit is set when a bad DLLP is
detected.
8 RPLYROVR RW1C 0x0
Sticky
Replay Number Rollover Status. This bit is set when a
replay number rollover has occurred indicating that the data
link layer has abandoned replays and has requested that
the link be retrained.
11:9 Reserved RO 0x0 Reserved field.
12 RPLYTO RW1C 0x0
Sticky
Replay Timer Time-Out Status. This bit is set when the
replay timer in the data link layer times out.
13 ADVISO-
RYNF
RW1C 0x0
Sticky
Advisory Non-Fatal Error Status. This bit is set when an
advisory non-fatal error is detected as described in Section
6.2.3.2.4 of the PCIe base 1.1 specification.
31:14 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 RCVERR RW 0x0
Sticky
Receiver Error Mask. When this bit is set, the correspond-
ing bit in the AERCES register is masked. When a bit is
masked in the AERCES register, the corresponding event is
not reported to the root complex.
5:1 Reserved RO 0x0 Reserved field.
6 BADTLP RW 0x0
Sticky
Bad TLP Mask. When this bit is set, the corresponding bit in
the AERCES register is masked. When a bit is masked in
the AERCES register, the corresponding event is not
reported to the root complex.
7 BADDLLP RW 0x0
Sticky
Bad DLLP Mask. When this bit is set, the corresponding bit
in the AERCES register is masked. When a bit is masked in
the AERCES register, the corresponding event is not
reported to the root complex.
8 RPLYROVR RW 0x0
Sticky
Replay Number Rollover Mask. When this bit is set, the
corresponding bit in the AERCES register is masked. When
a bit is masked in the AERCES register, the corresponding
event is not reported to the root complex.
11:9 Reserved RO 0x0 Reserved field.
12 RPLYTO RW 0x0
Sticky
Replay Timer Time-Out Mask. When this bit is set, the cor-
responding bit in the AERCES register is masked. When a
bit is masked in the AERCES register, the corresponding
event is not reported to the root complex.