IDT 89HPES24N3A, User Manual

Page: 97 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 3 April 10, 2008
Notes
Upstream Port (Port 0)
Note: In pdf format, clicking on a register name in the Register Definition column creates a jump
to the appropriate register. To return to the starting place in this table, click on the same register
name (in blue) in the register section.
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 9-11
0x002 Word P0_DID DID - Device Identification Register (0x002) on page 9-12
0x004 Word P0_PCICMD PCICMD - PCI Command Register (0x004) on page 9-12
0x006 Word P0_PCISTS PCISTS - PCI Status Register (0x006) on page 9-13
0x008 Byte P0_RID RID - Revision Identification Register (0x008) on page 9-14
0x009 3 Bytes P0_CCODE CCODE - Class Code Register (0x009) on page 9-14
0x00C Byte P0_CLS CLS - Cache Line Size Register (0x00C) on page 9-14
0x00D Byte P0_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 9-14
0x00E Byte P0_HDR HDR - Header Type Register (0x00E) on page 9-14
0x00F Byte P0_BIST BIST - Built-in Self Test Register (0x00F) on page 9-14
0x010 DWord P0_BAR0 BAR0 - Base Address Register 0 (0x010) on page 9-15
0x014 DWord P0_BAR1 BAR1 - Base Address Register 1 (0x014) on page 9-15
0x018 Byte P0_PBUSN PBUSN - Primary Bus Number Register (0x018) on page 9-15
0x019 Byte P0_SBUSN SBUSN - Secondary Bus Number Register (0x019) on page 9-15
0x01A Byte P0_SUBUSN SUBUSN - Subordinate Bus Number Register (0x01A) on page 9-
15
0x01B Byte P0_SLTIMER SLTIMER - Secondary Latency Timer Register (0x01B) on page
9-15
0x01C Byte P0_IOBASE IOBASE - I/O Base Register (0x01C) on page 9-16
0x01D Byte P0_IOLIMIT IOLIMIT - I/O Limit Register (0x01D) on page 9-16
0x01E Word P0_SECSTS SECSTS - Secondary Status Register (0x01E) on page 9-16
0x020 Word P0_MBASE MBASE - Memory Base Register (0x020) on page 9-17
0x022 Word P0_MLIMIT MLIMIT - Memory Limit Register (0x022) on page 9-17
0x024 Word P0_PMBASE PMBASE - Prefetchable Memory Base Register (0x024) on page
9-17
0x026 Word P0_PMLIMIT PMLIMIT - Prefetchable Memory Limit Register (0x026) on page
9-18
0x028 DWord P0_PMBASEU PMBASEU - Prefetchable Memory Base Upper Register (0x028)
on page 9-18
0x02C DWord P0_PMLIMITU PMLIMITU - Prefetchable Memory Limit Upper Register (0x02C)
on page 9-18
0x030 Word P0_IOBASEU IOBASEU - I/O Base Upper Register (0x030) on page 9-18
0x032 Word P0_IOLIMITU IOLIMITU - I/O Limit Upper Register (0x032) on page 9-19
0x034 Byte P0_CAPPTR CAPPTR - Capabilities Pointer Register (0x034) on page 9-19
Table 9.2 Upstream Port 0 Configuration Space Registers (Part 1 of 5)