IDT 89HPES24N3A, User Manual

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IDT Theory of Operation
PES24N3A User Manual 3 - 10 April 10, 2008
Notes
Port Interrupts
The upstream port, port 0, does not generate legacy interrupts or MSIs. Downstream ports support
generation of legacy interrupts and MSIs. The following are sources of downstream port interrupts and
MSIs.
– Downstream port’s hot-plug controller
– Link bandwidth notification capability (i.e., assertion of the LBWSTS or LABWSTS bits in the
PCIELSTS register when interrupt notification is enabled for these bits)
When a downstream port is configured to generate INTx messages, only INTA is used. When an
unmasked interrupt condition occurs, then an MSI or interrupt message is generated by the corresponding
port as described in Table 7.6. The removal of the interrupt condition occurs when unmasked status bit(s)
causing the interrupt are masked or cleared.
The PES24N3A assumes that all downstream port generated MSIs are targeted to the root and routes
these transactions to the upstream port. Configuring the address contained in a downstream port’s
MSIADDR and MSIADDRU registers to an address that does not route to the upstream port and generating
an MSI produces undefined results.
Legacy Interrupt Emulation
The PES24N3A supports legacy PCI INTx emulation. Rather than use sideband INTx signals, PCIe
defines two messages that indicate the assertion and negation of an interrupt signal. An Assert_INTx
message is used to signal the assertion of an interrupt signal and an Deassert_INTx message is used to
signal its negation.
The PES24N3A maintains an aggregated INTx state for each of the four interrupt signals (i.e., A through
D) at each port.
– The value of the INTA, INTB, INTC and INTD aggregated state for the entire switch may be deter-
mined by examining the corresponding field in the upstream port’s Interrupt Status (P0_INTSTS)
register.
– The aggregated INTx state for a downstream port may be determined by reading the corre-
sponding field in the port’s Interrupt Status (Px_INTSTS) register. This register contains the aggre-
gated state of interrupts generated by that port (i.e., hot-plug) plus interrupt messages received
from the downstream link partner. The interrupt state reflects the state of interrupts as seen by that
port (i.e., before downstream port interrupts are mapped to upstream port interrupts).
Unmasked
Interrupt
EN bit in
MSICAP
Register
INTXD bit
in PCICMD
Register
Actions
Asserted 1 X MSI message generated
0 0 Assert_INTA message request generated to switch
core
0 1 None
Negated 1 X None
0 0 Deassert_INTA message request generated to
switch core
0 1 None
Table 3.7 Downstream Port Interrupts