IDT 89HPES24N3A, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES24N3A User Manual 2 - 3 April 10, 2008
Notes
Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum Clock)
Initialization
A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES24N3A
during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation. Since the boot configuration vector is sampled only during a fundamental
reset sequence, the value of signals which make up the boot configuration vector is ignored during other
times and their state outside of a fundamental reset has no effect on the operation of the PES24N3A.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features may require configuration via an external serial EEPROM. The external serial EEPROM
allows modification of any bit in any software visible register. See Chapter 6, SMBus Interfaces, for more
information on the serial EEPROM.
The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a fundamental reset. The signals that may be over-
ridden are noted in Table 2.2. The state of all of the boot configuration signals in Table 2.2 sampled during
the most recent cold reset may be determined by reading the SWSTS register.
Signal Type Name/Description
CCLKDS I Common Clock Downstream. When the CCLKDS pin is
asserted, it indicates that a common clock is being used
between the downstream device and the downstream port.
CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted,
it indicates that a common clock is being used between the
upstream device and the upstream port.
MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates
that the master SMBus should operate at 100 KHz instead of
400 KHz. This value may not be overridden.
Table 2.2 Boot Configuration Vector Signals (Part 1 of 2)
PES24N3A
Port A
Port B
Port C
CCLKDS
CCLKUS
REFCLK0
REFCLK1
EP
EP
Root Complex
Low
Low
Clock Generator
Clock Generator
Clock Generator