IDT 89HPES24N3A, User Manual

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IDT Theory of Operation
PES24N3A User Manual 3 - 15 April 10, 2008
Notes
Address Routed TLPs
– TLPs whose address decoding indicates they are to route back to the port on which they were
received.
– TLPs received on the upstream port that match the upstream port’s address range but which do
not match a downstream port’s address range (i.e., TLPs that do not route through the
PES24N3A).
– TLPs that target a downstream port that is not enabled for such transactions.
• For prefetchable memory and non-prefetchable memory transactions, the Memory Access
Enable (MAE) bit must be set in the PCI Command (PCICMD) register.
• For I/O transactions, the I/O Access Enable (IOAE) bit must be set in the PCI Command
(PCICMD) register.
– Memory and IO requests from downstream ports that target the upstream port and the Bus Master
Enable (BME) bit is cleared in the upstream port’s PCICMD register.
– Memory and IO requests received on downstream ports and the Bus Master Enable (BME) bit is
cleared in the downstream port’s PCICMD register.
– A VGA route from a VGA enabled downstream port.
Configuration Requests (Routed by ID)
– Type 0 requests that arrive on a downstream port.
– Type 1 requests that arrive on a downstream port.
– Type 1 requests that do not route through the upstream port’s PCI-to-PCI bridge.
– Type 1 requests that are converted to Type 0 requests at the upstream port but which do not target
an enabled downstream port device number (i.e., target a PCI-to-PCI bridge device number that
doesn’t exist).
– Type 1 requests that route through the PES24N3A target a downstream port’s link partner (i.e.,
are converted to a Type 0 request at the downstream port), and which do not target device zero.
Note that this check may be disabled by the DDDNC bit in the SWCTL register. See section
SWCTL - Switch Control (0x404) on page 9-51 for more information.
Completions (Routed by ID)
– Completions that attempt to route back onto the link on which they were received.
– Completions that do not have a valid route through the PES24N3A.
– All completions that terminate within the PES24N3A (i.e., ones that target the upstream port bus
number or any device/function on the virtual PCI bus within the switch) are treated as unexpected
completions.
ID Routed Messages
– Messages that attempt to route back onto the link on which they were received.
– Messages that do not have a valid route through the PES24N3A.
– Messages that target a downstream port device number that does not exist.
– A non Vendor Defined Type 1 message which targets an enabled PES24N3A port (i.e., PCI-to-
PCI bridge). Vendor Defined Type 1 messages received by a PES24N3A port are silently
discarded.
– A non Vendor Defined Type 1 message which is received by the upstream port.
Switch Specific Error Detection and Handling
This section describes PES24N3A-specific error detection and handling. Since these mechanisms are
outside of the PCIe base 1.1 specification, the PES24N3A-specific initialization and error handling code
may be required to take full advantage of these features.