IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 27 April 10, 2008
Notes
PCIESCAP - PCI Express Slot Capabilities (0x054)
10 TERR RO 0x0 Training Error. In PCIe base 1.0a when set, this bit indi-
cates that a link training error has occurred.
The value of this field is undefined in PCIe base 1.1
11 LTRAIN RO 0x0 Link Training . When set, this bit indicates that link training
is in progress.
12 SCLK RWL HWINIT Slot Clock Configuration . When set, this bit indicates that
the component uses the same physical reference clock that
the platform provides. The initial value of this field is the
state of the CCLKUS signal for the upstream port and the
CCLKDS signal for downstream ports. The serial EEPROM
may override these default values.
13 DLLLA RO 0x0 Data Link Layer Link Active . This bit indicates the status
for the data link control and management state machine.
This bit is always zero if the DLLLA bit in the PCIELCAP
register is not set.
0x0 - (notactive) Data link layer not active state
0x1 - (active) Data link layer active state.
14 LBWSTS RW1C 0x0 Link Bandwidth Management Status . This bit is set to
indicate that either of the following have occurred without
the link transitioning through the DL_Down state.
A link retraining initiated by setting the LRET bit in the
PCIELCTL register has completed.
The PHY has autonomously changed link speed or width to
attempt to correct unreliable link operation either through an
LTSSM time-out or a higher level process.
If the LBN field in the PCIELCAP register is cleared, this
field is hardwired to zero.
This field is read-only zero in PCIe 1.1 mode.
15 LABWSTS RW1C 0x0 Link Autonomous Bandwidth Status . This bit is set to
indicate that either that the PHY has autonomously changed
link speed or width for reasons other than to attempt to cor-
rect unreliable link operation.
This bit is set when a downstream switch port receives eight
consecutive TS1 or TS2 ordered sets with the Autonomous
Change bit set.
If the LBN field in the PCIELCAP register is cleared, this
field is hardwired to zero.
This field is read-only zero in PCIe 1.1 mode.
Bit
Field
Field
Name
Type
Default
Value
Description
0 ABP RWL 0x0 Attention Button Present . This bit is set when the Attention
Button is implemented for the port.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
1 PCP RWL 0x0 Power Control Present . This bit is set when a Power Con-
troller is implemented for the port.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
Bit
Field
Field
Name
Type
Default
Value
Description