IDT 89HPES24N3A, User Manual

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IDT Theory of Operation
PES24N3A User Manual 3 - 16 April 10, 2008
Notes
Switch Time-Outs
The switch core discards any TLP that reaches the head of an IFB queue and is more than 64 seconds
old. This includes posted, non-posted, completion and inserted TLPs. Although this feature is enabled by
default, it may be disabled by setting the Enable Switch Time-outs (ETO) bit in a port’s Switch Time-Out
Control (SWTOCTL) register.
Whenever a TLP is discarded by a port due to a switch time-out, a bit corresponding to the type of TLP
that was discarded is set in port’s Switch Time-Out Status (SWTOSTS) register. In addition, a saturating
count field corresponding to the type of TLP that was discarded is incremented in the port’s Switch Time-
Out Count (SWTOCNT) register. These saturating count fields are atomically cleared when read.
Corresponding to each TLP type that may be discarded in the SWTOSTS register is an associated field
in the Switch Time-Out Reporting Control (SWTORCTL) register that controls the manner in which a
dropped TLP of that type is reported. Error message reporting due to dropped TLPs is considered an inter-
nally generated error message and thus may be masked in the same manner as other internally generated
error messages with the SERR Enable (SERRE) bit in the PCI Command (PCICMD) register and the error
reporting enables (i.e., CERN, NFEREN, FEREN, and UREREN bits) in the PCI Express Device Control
(PCIEDCTL) register.
If error reporting is enabled, an error message is generated when a status bit transitions from a zero to a
one (i.e., is set) in the SWTOSTS register. A subsequent error of the same type is not reported until soft-
ware clears the corresponding status bit and it is again set.
Following a fundamental reset, discarded posted and inserted TLPs are reported with an
ERR_NONFATAL message. Discarded non-posted and completion TLPs are not reported by default since
the requester’s completion timer will detect the loss of a TLP of this type. The default error reporting policy
my be modified by the root, serial EEPROM, or slave SMBus master.
If during processing of a TLP with broadcast routing a switch core time-out occurs, then the switch core
will abort processing of the TLP. This may result in the broadcast TLP being transmitted on some but not all
downstream pots.
End-to-End Parity Checking
PCI Express provides reliable hop-by-hop communication between interconnected devices, such as
roots, switches, and endpoints, by utilizing a 32-bit Link CRC (LCRC), sequence numbers, and a link level
retransmission protocol. While this mechanism provides reliable communication between interconnected
devices, it does not protect against corruption that may occur inside of a device. PCI Express defines an
optional end-to-end data integrity mechanism that consists of appending a 32-bit end-to-end CRC (ECRC)
computed at the source over the invariant fields of a Transaction Layer Packet (TLP) that is checked at the
ultimate destination of the TLP. While this mechanism provides end-to-end error detection, unfortunately it
is an optional PCI Express feature and has not been implemented in many North bridges and endpoints. In
addition, the ECRC mechanism does not cover variant fields within a TLP.
Since deep sub-micron devices are known to be susceptible to single-event-upsets, a mechanism is
desired that detects errors that occur within a PCI express switch. The PES24N3A parity protects all TLPs
in the switch, thus enabling corruption that may occur inside of the device to be detected and reported even
in systems that do not implement ECRC.
Data flowing into the PES24N3A is protected by the LCRC. Within the Data Link (DL) layer of the switch
ingress port, the LCRC is checked and 32-bit DWord even parity is computed on the received TLP data. If
an LCRC error is detected at this point, the link level retransmission protocol is used to recover from the
error by forcing a retransmission by the link partner. As the TLP flows through the switch, its alignment or
contents may be modified. In all such cases, parity is updated and not recomputed. Hence, any error that
occurs is propagated and not masked by a parity regeneration. When the TLP reaches the DL layer of the
switch egress port, parity is checked and in parallel a LCRC is computed. If the TLP is parity error free, then
the LCRC and TLP contents are known to be correct and the LCRC is used to protect the packet through
the lower portion of the DL layer, PHY layer, and link transmission.