IDT 89HPES24N3A, User Manual

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IDT SMBus Interfaces
PES24N3A User Manual 6 - 7 April 10, 2008
Notes
The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander zero:
– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through
I/O-0.7) to I/O expander register 2.
– Write the default value of the outputs bits on the upper eight I/O expander pins (i.e.,I/O-1.0 through
I/O-1.7) to I/O expander register 3.
– Write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– Write value 0x0 to I/O expander register 5 (no inversion in IO-1).
– Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-
0.0 through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select inputs/outputs in the upper eight I/O expander bits (i.e., I/
O-1.0 through I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7).
– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7).
The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander two
(i.e., the one that contains hot-plug signals and power good inputs):
– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through
I/O-0.7) to I/O expander register 2.
– Write value 0x0 to I/O expander register 4 (no inversion in IO-0).
– Write value 0x0 to I/O expander register 5 (no inversion in IO-1).
– Write the configuration value to select inputs/outputs in the lower eight I/O expander bits (i.e., I/O-
0.0 through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select all inputs upper eight I/O expander bits (i.e.,I/O-1.0 through
I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7).
– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7).
The following I/O expander configuration sequence is issued by the PES24N3A to I/O expander four:
– Write the default value of the outputs bits on the lower eight I/O expander pins (i.e.,I/O-0.0 through
I/O-0.7) to I/O expander register 2.
– Write the default value of the outputs bits on the upper eight I/O expander pins (i.e.,I/O-1.0 through
I/O-1.7) to I/O expander register 3.
– Write value 0x0 to I/O expander register 4 (no inversion in IO-0)
– Write value 0x0 to I/O expander register 5 (no inversion in IO-1).
– Write the configuration value to select outputs in the lower eight I/O expander bits (i.e., I/O-0.0
through I/O-0.7) to I/O expander register 6.
– Write the configuration value to select outputs in the upper eight I/O expander bits (i.e., I/O-1.0
through I/O-1.7) to I/O expander register 7.
– Read value of I/O expander register 0 to obtain the current state of the lower eight I/O expander
bits (i.e., I/O-0.0 through I/O-0.7).
– Read value of I/O expander register 1 to obtain the current state of the upper eight I/O expander
bits (i.e., I/O-1.0 through I/O-1.7).
While the I/O expander is enabled, the PES24N3A maintains the I/O bus expander signals and the
PES24N3A internal view of the hot-plug signals in a consistent state. This means that whenever that I/O
bus expander state and the PES24N3A internal view of the signal state differs, an SMBus transaction is
initiated by the PES24N3A to resolve the state conflict.