IDT 89HPES24N3A, User Manual

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IDT Hot-Plug and Hot-Swap
PES24N3A User Manual 8 - 3 April 10, 2008
Notes
The remainder of this section discusses the use of the PES24N3A in an application involving an add-in
card hot-plugged into a downstream slot. Associated with each downstream port in the PES24N3A is a hot-
plug controller. The hot-plug controller may be enabled by setting the HPC bit in the PCI Express Slot Capa-
bilities (PCIESCAP) register associated with that port during configuration (e.g., via serial EEPROM).
The PES24N3A allows sensor inputs and indicator outputs to be located next to the slot or on the plug in
the module. Regardless of the physical location, the indicators are controlled by the PES24N3A’s down-
stream port. Table 8.1 lists the hot-plug inputs and outputs that may be associated with a slot. When
enabled during configuration in the PCIESCAP register, these inputs and outputs are made available to
external logic using an external I/O expander located on the master SMBus interface. The PES24N3A only
supports Presence Detect Signalling via a pin assertion. It does not support In-band Presence Detect.
Since the polarity of hot-plug signals has been defined differently in various specifications, each hot-plug
signal has a corresponding control bit in the Hot-Plug Configuration Control (HPCFGCTL) that allows the
polarity of that signal to be inverted. Inversion affects the corresponding signal in all ports.
When a one is written to the EIC bit in the PCIESCTL register, then the PxILOCKP signal is pulsed with
a pulse length greater than 100 ms and less than 150 ms (i.e., it transactions from negated to asserted,
maintains an asserted state for 100 to 150 ms, and then transitions back to negated). When the Toggle
Electromechanical Interlock Control. (TEMICTL) bit in the HPCFGCTL register is set, writing a one to the
EIC bit inverts the state of the PxILOCKP signal.
When the Replace MRL Status with EMIL Status (RMRLWEMIL) bit is set in the HPCFGCTL register,
then the port’s PxMRLN input is used as the electromechanical state input. The state of this input is used as
the state of the electromechanical interlock state obtained by reading the Electromechanical Interlock
Status (EIS) bit in the PCI Express Slot Status (PCIESSTS) register. In this mode, the state of the manually-
operated Retention Latch Sensor State (MRLSS) status is always reported as closed (i.e., zero). When the
RMRLWEMIL bit is cleared, the EIS bit state in the PCIESSTS register always returns the value of the
corresponding PxILOCKP I/O expander signal output.
When the MRL Automatic Power Off (MRLPWROFF) bit is set in the HPCFGCTL register and the
Manual Retention Latch Present (MRLP) bit is set in the PCI Express Slot Capability (PCIESCAP) register,
then power to the slot is automatically turned off when the MRL sensor indicates that the MRL is open. This
occurs regardless of the state of the Power Controller Control (PCC) bit in the PCI Express Slot Control
(PCIESCTL) register.
Downstream port reset outputs are described in section Downstream Port Reset Outputs on page 2-8.
Signal Type Name/Description
PxAPN I Port x
1
Attention Push button Input.
1.
x corresponds to downstream port number (i.e., 2 and 4).
PxPDN I Port x Presence Detect Input.
PxPFN I Port x Power Fault Input.
PxMRLN I Port x Manually-operated Retention Latch (MRL) Input.
PxAIN O Port x Attention Indicator Output.
PxPIN O Port x Power Indicator Output.
PxPEP O Port x Power Enable Output.
PxILOCKP O Port x Electromechanical Interlock.
PxPWRGDN I Port x Power Good Input (asserted when slot power is good).
PxRSTN
2
2.
This signal is a GPIO pin alternate function and is not available as an I/O expander output.
O Port x Reset Output.
Table 8.1 Downstream Port Hot-Plug Signals