IDT 89HPES24N3A, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES24N3A User Manual 2 - 8 April 10, 2008
Notes
When a downstream secondary bus reset occurs, the following sequence is executed.
1. If the corresponding downstream port’s link is up, TS1 ordered sets with the hot reset bit set are
transmitted
2. All TLPs received from corresponding downstream port and queued in the PES24N3A are
discarded.
3. Wait for the Secondary Bus Reset (SRESET) bit in the Bridge Control Register (BCTL) to clear.
4. Normal downstream port operation begins.
The operation of the upstream port is unaffected by a downstream secondary bus reset. The operation
of other downstream ports is unaffected by a downstream secondary bus reset. During a downstream
secondary bus reset, Type 0 configuration read and write transactions that target the downstream port
complete normally. During a downstream secondary bus reset, all TLPs destined to the secondary side of
the downstream port’s PCI-to-PCI bridge are treated as unsupported requests.
The operation of the slave SMBus interface is unaffected by a downstream secondary bus reset.
Downstream Port Reset Outputs
Individual downstream port reset outputs (PxRSTN) are provided as GPIO pin alternate functions.
Following a fundamental reset, all of the GPIO pins default to GPIO inputs. Therefore, the downstream port
resets are tri-stated. A system designer should use a pull-down on these signals if they are used as reset
outputs.
The PES24N3A ensures through hardware that the minimum PxRSTN assertion pulse width is no less
than 200 µS.
Downstream port reset outputs can be configured to operate in one of three modes. These modes are:
power enable controlled reset output, power good controlled reset output, and hot reset controlled output.
The downstream port reset output mode is determined by the Reset Mode (RSTMODE) field in the
Hot-Plug Configuration Control (HPCFGCTL) register.
Power Enable Controlled Reset Output
In this mode, a downstream port reset output state is controlled as a side effect of slot power being
turned on or off. The operation of this mode is illustrated in Figure 2.6. A downstream port’s slot power is
controlled by the Power Controller Control (PCC) bit in the PCI Express Slot Control (PCIESCTL) register.
Figure 2.6 Power Enable Controlled Reset Output Mode Operation
While slot power is disabled, the corresponding downstream port reset output is asserted. When slot
power is enabled by writing a zero to the PCC bit, the Port x Power Enable Output (PxPEP) is asserted and
then power to the slot is enabled and the corresponding downstream port reset output is negated. The time
between the assertion of the PxPEP signal and the negation of the PxRSTN signal is controlled by the
value in the Slot Power to Reset Negation (PWR2RST) field in the HPCFGCTL register.
PxPEP
PxRSTN
T
PWR2RST
T
RST2PWR