IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 22 April 10, 2008
Notes
PCIEDCTL - PCI Express Device Control (0x048)
12 ABP RO 0x0 Attention Button Present. In PCIe base 1.1 when set, this
bit indicates that an Attention Button is implemented on the
card/module.
The value of this field is undefined in PCIe base 1.1
13 AIP RO 0x0 Attention Indicator Present. In PCIe base 1.1 when set,
this bit indicates that an Attention Indicator is implemented
on the card/module.
The value of this field is undefined in PCIe base 1.1
14 PIP RO 0x0 Power Indicator Present. In PCIe base 1.1 when set, this
bit indicates that a Power Indicator is implemented on the
card/module.
The value of this field is undefined in PCIe base 1.1
15 RBERR RO 0x1 Role Based Error Reporting. This bit is set to indicate that
the PES24N3A supports error reporting as defined in the
PCIe base 1.1 and 2.0 specifications.
17:16 Reserved RO 0x0 Reserved field.
25:18 CSPLV RO 0x0 Captured Slot Power Limit Value. This field in combination
with the Slot Power Limit Scale value, specifies the upper
limit on power supplied by the slot. Power limit (in Watts)
calculated by multiplying the value in this field by the value
in the Slot Power Limit Scale field.
The value of this field is set by a Set_Slot_Power_Limit
Message and is only applicable for the upstream port. This
field is always zero in downstream ports.
27:26 CSPLS RO 0x0 Captured Slot Power Limit Scale. This field specifies the
scale used for the Slot Power Limit Value.
The value of this field is set by a Set_Slot_Power_Limit
Message and is only applicable for the upstream port. This
field is always zero in downstream ports.
0 - (v1) 1.0x
1 -(v1p1) 0.1x
2 - (v0p01) 0.01x
3 -(v0p001x) 0.001x
31:28 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 CEREN RW 0x0 Correctable Error Reporting Enable . This bit controls
reporting of correctable errors.
1 NFEREN RW 0x0 Non-Fatal Error Reporting Enable . This bit controls report-
ing of non-fatal errors.
2 FEREN RW 0x0 Fatal Error Reporting Enable . This bit controls reporting of
fatal errors.
3 URREN RW 0x0 Unsupported Request Reporting Enable . This bit controls
reporting of unsupported requests.
4 ERO RO 0x0 Enable Relaxed Ordering . When set, this bit enables
relaxed ordering. The switch never sets the relaxed ordering
bit in transactions it initiates as a requester.
Bit
Field
Field
Name
Type
Default
Value
Description