IDT 89HPES24N3A, User Manual

Page: 129 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 35 April 10, 2008
Notes
MSIADDR - Message Signaled Interrupt Address (0x0D4)
MSIUADDR - Message Signaled Interrupt Upper Address (0x0D8)
16 EN RW 0x0 Enable. This bit enables MSI.
0x0 -(disable) disabled
0x1 -(enable) enabled
19:17 MMC RO 0x0 Multiple Message Capable. This field contains the number
of requested messages.
22:20 MME RW 0x0 Multiple Message Enable. Hardwired to one message.
23 A64 RO 0x1 64-bit Address Capable. The bridge is capable of generat-
ing messages using a 64-bit address.
31:24 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 Reserved RO 0x0 Reserved field.
31:2 ADDR RW 0x0 Message Address . This field specifies the lower portion of
the DWORD address of the MSI memory write transaction.
The PES24N3A assumes that all downstream port gener-
ated MSIs are targeted to the root and routes these trans-
actions to the upstream port. Configuring the address
contained in a downstream port’s MSIADDR and MSIAD-
DRU registers to an address that does not route to the
upstream port and generating an MSI produces undefined
results.
Bit
Field
Field
Name
Type
Default
Value
Description
31:0 UADDR RW 0x0 Upper Message Address . This field specifies the upper
portion of the DWORD address of the MSI memory write
transaction. If the contents of this field are non-zero, then
64-bit address is used in the MSI memory write transaction.
If the contents of this field are zero, then the 32-bit address
specified in the MSIADDR field is used.
The PES24N3A assumes that all downstream port gener-
ated MSIs are targeted to the root and routes these trans-
actions to the upstream port. Configuring the address
contained in a downstream port’s MSIADDR and MSIAD-
DRU registers to an address that does not route to the
upstream port and generating an MSI produces undefined
results.
Bit
Field
Field
Name
Type
Default
Value
Description