IDT 89HPES24N3A, User Manual

Page: 32 / 168

IDT Clocking, Reset, and Initialization Clock Operation
PES24N3A User Manual 2 - 4 April 10, 2008
Notes
Reset
The PES24N3A defines four reset categories:
– fundamental reset
– hot reset
– upstream secondary bus reset
– downstream secondary bus reset.
A fundamental reset causes all logic in the PES24N3A to be returned to its initial state. A hot reset
causes all logic in the PES24N3A to be returned to its initial state, but does not cause the state of register
fields denoted as “sticky” to be modified. An upstream secondary bus reset causes all devices on the virtual
PCI bus to be hot reset except the upstream port (i.e., upstream PCI to PCI bridge). A downstream
secondary bus reset causes a hot reset to be propagated on the corresponding external secondary bus link.
There are two sub-categories of fundamental reset: cold reset and warm reset. A cold reset occurs
following a device being powered on and assertion of PERSTN. A warm reset is a fundamental reset that
occurs without removal of power.
Fundamental Reset
A fundamental reset may be initiated by any of the following conditions:
– A cold reset initiated by a power-on and the assertion of the PCI Express Reset (PERSTN) input
pin.
– A warm reset initiated by the assertion of the PCI Express Reset (PERSTN) input pin while power
is on.
– A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch
Control (SWCTL) register.
PERSTN I Fundamental Reset. Assertion of this signal resets all logic
inside PES24N3A and initiates a PCI Express fundamental
reset.
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express
fundamental reset, PES24N3A executes the reset procedure
and remains in a reset state with the Master and Slave
SMBuses active. This allows software to read and write regis-
ters internal to the device before normal device operation
begins. The device exits the reset state when the RSTHALT bit
is cleared in the SWCTL register by an SMBus master.
SWMODE[3:0] I Switch Mode. These configuration pins determine the
PES24N3A switch operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0xF - Reserved
Signal Type Name/Description
Table 2.2 Boot Configuration Vector Signals (Part 2 of 2)