IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 29 April 10, 2008
Notes
PCIESCTL - PCI Express Slot Control (0x058)
Bit
Field
Field
Name
Type
Default
Value
Description
0 ABPE RW 0x0 Attention Button Pressed Enable . This bit when set
enables generation of a Hot-Plug interrupt or wake-up event
on an attention button pressed event.
This bit is read-only and has a value of zero when the corre-
sponding capability is not enabled in the PCIESCAP regis-
ter.
1 PFDE RW 0x0 Power Fault Detected Enable . This bit when set enables
the generation of a Hot-Plug interrupt or wake-up event on a
power fault event.
This bit is read-only and has a value of zero when the corre-
sponding capability is not enabled in the PCIESCAP regis-
ter.
2 MRLSCE RW 0x0 MRL Sensor Change Enable . This bit when set enables
the generation of a Hot-Plug interrupt or wake-up event on a
MRL sensor change event.
This bit is read-only and has a value of zero when the corre-
sponding capability is not enabled in the PCIESCAP regis-
ter.
3 PDCE RW 0x0 Presence Detected Changed Enable . This bit when set
enables the generation of a Hot-Plug interrupt or wake-up
event on a presence detect change event.
4 CCIE RW 0x0 Command Complete Interrupt Enable . This bit when set
enables the generation of a Hot-Plug interrupt when a com-
mand is completed by the Hot-Plug Controller.
This bit is read-only and has a value of zero when the corre-
sponding capability is not enabled in the PCIESCAP regis-
ter.
5 HPIE RW 0x0 Hot-Plug Interrupt Enable . This bit when set enables gen-
eration of a Hot-Plug interrupt on enabled Hot-Plug events.
This bit is read-only and has a value of zero when the corre-
sponding capability is not enabled in the PCIESCAP regis-
ter.
7:6 AIC RW 0x3 Attention Indicator Control . When read, this register
returns the current state of the Attention Indicator. Writing to
this register sets the indicator.
This bit is read-only and has a value of zero when the corre-
sponding capability is not enabled in the PCIESCAP regis-
ter.
This field is always zero if the ATTIP bit is cleared in the
PCIESCAP register.
0x0 -(reserved) Reserved
0x1 -(on) On
0x2 -(blink) Blink
0x3 -(off) Off