IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 39 April 10, 2008
Notes
AERUESV - AER Uncorrectable Error Severity (0x10C)
16 UECOMP RW 0x0
Sticky
Unexpected Completion Mask. When this bit is set, the
corresponding bit in the AERUES register is masked. When
a bit is masked in the AERUES register, the corresponding
event is not logged in the advanced capability structure and
an error is not reported to the root complex.
17 RCVOVR RW 0x0
Sticky
Receiver Overflow Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit
is masked in the AERUES register, the corresponding event
is not logged in the advanced capability structure and an
error is not reported to the root complex.
18 MAL-
FORMED
RW 0x0
Sticky
Malformed TLP Mask. When this bit is set, the correspond-
ing bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is
not logged in the advanced capability structure and an error
is not reported to the root complex.
19 ECRC RW 0x0
Sticky
ECRC Mask. When this bit is set, the corresponding bit in
the AERUES register is masked. When a bit is masked in
the AERUES register, the corresponding event is not logged
in the advanced capability structure and an error is not
reported to the root complex.
20 UR RW 0x0
Sticky
UR Mask. When this bit is set, the corresponding bit in the
AERUES register is masked. When a bit is masked in the
AERUES register, the corresponding event is not logged in
the advanced capability structure and an error is not
reported to the root complex.
31:21 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 UDEF RW 0x0
Sticky
Undefined. This bit is no longer used in this version of the
specification.
3:1 Reserved RO 0x0 Reserved field.
4 DLPERR RW 0x1
Sticky
Data Link Protocol Error Severity. If the corresponding
event is not masked in the AERUEM register, then when the
event occurs, this bit controls the severity of the reported
error. If this bit is set, the event is reported as a fatal error.
When this bit is cleared, the event is reported as an uncor-
rectable error.
5 SDOENERR RW 0x1
Sticky
Surprise Down Error Status. If the corresponding event is
not masked in the AERUEM register, then when the event
occurs, this bit controls the severity of the reported error. If
this bit is set, the event is reported as a fatal error. When
this bit is cleared, the event is reported as an uncorrectable
error.
11:6 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description