IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 20 April 10, 2008
Notes
BCTRL - Bridge Control Register (0x03E)
Bit
Field
Field
Name
Type
Default
Value
Description
0 PERRE RW 0x0 Parity Error Response Enable. This bit controls the
bridges response to poisoned TLPs on the secondary inter-
face.
0x0 - (ignore) Ignore poisoned TLPs (i.e., parity errors) on
the secondary interface.
0x1 - (report) Enable poisoned TLP (i.e., parity error) detec-
tion and reporting on the secondary interface of the
bridge.
1 SERRE RW 0x0 System Error Enable. This bit controls forwarding of
ERR_COR, ERR_NONFATAL, ERR_FATAL from the sec-
ondary interface of the bridge to the primary interface.
Note that error reporting must be enabled in the Command
register or PCI Express Capability structure, Device Control
register for errors to be reported on the primary interface.
0x0 - (ignore) Do not forward errors from the secondary to
the primary interface.
0x1 - (report) Enable forwarding of errors from secondary to
the primary interface.
2 ISAEN RW 0x0 ISA Enable. This bit controls the routing of ISA I/O transac-
tions.
0 - (disable) Forward downstream all I/O addresses in the
address range defined by the I/O base and I/O limit reg-
isters.
1 - (enable) Forward upstream ISA I/O addresses in the
address range defined by the I/O base and I/O limit reg-
isters that are in the first 64 KB of PCI I/O address space
(top 768 bytes of each 1-KB block).
3 VGAEN RW 0x0 VGA Enable. Controls the routing of processor-initiated
transactions targeting VGA.
0 - (block) Do not forward VGA compatible addresses from
the primary interface to the secondary interface
1 -(forward) Forward VGA compatible addresses from the
primary to the secondary interface.
4 VGA16EN RW 0x0 VGA 16-bit Enable. This bit only has an effect when the
VGAEN bit is set in this register.
This read/write bit enables system configuration software to
select between 10-bit and 16-bit I/O space decoding for
VGA transactions.
0 - (bit10) Perform 10-bit decoding. I/O space aliasing
occurs in this mode.
1 -(bit16) Perform 16-bit decoding. No I/O space aliasing
occurs in this mode.
5 Reserved RO 0x0 Reserved field.
6 SRESET RW 0x0 Secondary Bus Reset. Setting this bit triggers a secondary
bus reset.
In the upstream port, setting this bit initiates a upstream sec-
ondary bus reset.
In a downstream port, setting this bit initiates a secondary
bus reset.
15:7 Reserved RO 0x0 Reserved field.