IDT 89HPES24N3A, User Manual

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IDT Theory of Operation
PES24N3A User Manual 3 - 17 April 10, 2008
Notes
If a parity error is detected by the DL layer of an egress port, then the TLP is nullified by inverting the
computed LCRC and ending the packet with an EDB symbol. Nullified TLPs received by the link-partner are
discarded. In addition to nullifying the TLP, the End-to-End Parity Error (EEPE) bit is set in the Switch parity
Error Status (SWPESTS) register, and the saturating End-to-End Parity Error Count (EEPEC) field is incre-
mented in the Switch Parity Error Count (SWPECNT) register. The EEPEC field is atomically cleared when
read.
All internal memories used to store TLP data within the PES24N3A are Dword even parity protected.
Parity errors in these memories are propagated and reported using the end-to-end parity protection mecha-
nism.
The End-to-End Parity Error Reporting (EEPE) field in the Switch Parity Error Reporting Control
(SWPERCTL) register controls the manner in which end-to-end parity errors are reported. If error reporting
is enabled, an error message is generated when the EEPE bit in the SWPESTS register transitions from a
zero to a one. A subsequent error of the same type is not reported until software clears the corresponding
status bit and it is again set. End-to-end parity checking at a port may be disabled by setting the Disable
End-to-End Parity Checking (DEEPC) bit in the Switch Parity Error Control (SWPECTL) register.
Parity generation can never be disabled at a port. However, to facilitate parity generation and checking
testing a mechanism exists to generate bad parity. When the Generate Bad End-to-End Parity (GBEEP) bit
is set in the SWPECTL register, bad (i.e., inverted) parity is generated for all Dwords of a TLP when the
length field in the TLP header matches the value of the Length (LENGTH) field in the SWPECTL register.
TLPs whose header length field does not match the LENGTH field are passed to the switch core with
correct parity.
Following a fundamental reset, end-to-end parity checking is enabled and errors are reported with an
ERR_NONFATAL message to the root. The default error reporting policy may be modified by the root, serial
EEPROM, or slave SMBus master.
In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed
by the switch (e.g., a configuration requests and responses). Whenever a TLP is produced by the switch,
parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they
flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP
is discarded and an error is reported using the mechanism described above.
This means that a parity error reported at a switch port cannot be definitively used to identify the location
at which the error occurred as the error may have occurred when parity as generated at another port, in the
switch core, or may have been generated locally (i.e., for ingress TLPs to the switch core which are
consumed by the port such as Type 0 configuration read requests on the upstream port).
TLP Processing
The PES24N3A supports two forms of very basic processing on TLPs that flow through the switch.
Since TLP processing modifies the contents of a TLP, it may not be used in systems that employ ECRC
since ECRC is not recomputed after TLP modifications. When the Force Relaxed Ordering (FRO) bit is set
in the TLP Processing Control (TLPPCTL) register, the value of the relaxed ordering attribute is set to the
value dictated by the Relaxed Ordering Modification (ROM) field in the TLPPCTL register. This transforma-
tion is only performed on TLPs in which the relaxed ordering attribute is applicable.
The relaxed ordering attribute is applicable to all TLPs except: configuration requests, I/O requests,
memory requests that are Message Signaled Interrupts (MSIs), and Message requests (except where
specifically permitted). Since MSIs cannot be distinguished from memory write transactions by the switch,
the relaxed ordering attribute of MSIs will be modified.
When the Force No-Snoop (FNS) bit is set in the TLP Processing Control (TLPPCTL) register, the value
of the no-snoop attribute is set to the value dictated by the No-Snoop Modification (NSM) field in the
TLPPCTL register. This transformation is only performed on TLPs in which the no-snoop attribute is appli-
cable. The no-snoop attribute is applicable to all TLPs except: configuration requests, I/O requests, memory