IDT 89HPES24N3A User Manual Download Page 59

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IDT Link Operation

PES24N3A User Manual

4 - 3

April 10, 2008

Notes

Figure 4.2 Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4)

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24N3A

lane 0

lane 1

lane 2

lane 3

(a) x4 Port without lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24N3A

lane 3

lane 2

lane 1

lane 0

(b) x4 Port with lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24N3A

lane 0

lane 1

(c) x2 Port without lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24N3A

lane 1

lane 0

(d) x2 Port with lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24N3A

lane 0

(e) x1 Port without lane reversal

PExRP[0]

PExRP[1]

PExRP[2]

PExRP[3]

PExRP[4]

PExRP[5]

PExRP[6]

PExRP[7]

PES24N3A

lane 0

(f) x1 Port with lane reversal

Summary of Contents for 89HPES24N3A

Page 1: ...6024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2008 Integrated Device Technology Inc IDT 89HPES24N3A PCI Express Switch...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...eature including polarity inversion link width negotiation and lane reversal Chapter 4 Switch Operation discusses the procedure for forwarding PCIe TLPs between switch ports Chapter 5 General Purpose...

Page 4: ...or hexadecimal formats will be used The binary format is as follows 0bDDD where D represents either 0 or 1 the hexadecimal format is as follows 0xDD where D represents the hexadecimal digit s otherwis...

Page 5: ...e Reading the value will automatically cause the register bit to be reset to zero Writing to a RC location has no effect Read Clear and Write RCW Software can read the register bits with this attribut...

Page 6: ...ET field is in BCTL register not the SWCTL register April 10 2008 In the About section Table 2 changed SYSCNTL to SWCTL In Chapter 9 changed default value for VER field in PCIECAP register from 0x2 to...

Page 7: ...VID 1 5 Device Serial Number Enhanced Capability 1 5 Pin Description 1 6 Pin Characteristics 1 9 Clocking Reset and Initialization Introduction 2 1 Initialization 2 3 Reset 2 4 Fundamental Reset 2 4 H...

Page 8: ...th Negotiation 4 1 Lane Reversal 4 1 Link Retraining 4 4 Link Down 4 5 Slot Power Limit Support 4 5 Upstream Port 4 5 Downstream Port 4 5 Link States 4 5 Active State Power Management 4 6 Link Status...

Page 9: ...Structure 9 34 Subsystem ID and Subsystem Vendor ID 9 36 Extended Configuration Space Access Registers 9 36 Advanced Error Reporting AER Enhanced Capability 9 37 Device Serial Number Enhanced Capabili...

Page 10: ...IDT Table of Contents PES24N3A User Manual iv April 10 2008 Notes...

Page 11: ...Function 5 1 Table 5 2 GPIO Pin Configuration 5 1 Table 6 1 Serial EEPROM SMBus Address 6 2 Table 6 2 PES24N3A Compatible Serial EEPROMs 6 3 Table 6 3 Serial EEPROM Initialization Errors 6 5 Table 6 4...

Page 12: ...IDT List of Tables PES24N3A User Manual vi April 10 2008 Notes...

Page 13: ...ization Sequence Format 6 3 Figure 6 3 Sequential Double Word Initialization Sequence Format 6 4 Figure 6 4 Configuration Done Sequence Format 6 4 Figure 6 5 Slave SMBus Command Code Format 6 12 Figur...

Page 14: ...IDT List of Figures PES24N3A User Manual viii April 10 2008 Notes...

Page 15: ...ed Configuration Space Access Data 0x0FC 9 37 EEPROMINTF Serial EEPROM Interface 0x42C 9 56 EROMBASE Expansion ROM Base Address Register 0x038 9 19 GPECTL General Purpose Event Control 0x450 9 58 GPES...

Page 16: ...Register 0x028 9 18 PMCAP PCI Power Management Capabilities 0x0C0 9 33 PMCSR PCI Power Management Control and Status 0x0C4 9 34 PMLIMIT Prefetchable Memory Limit Register 0x026 9 18 PMLIMITU Prefetch...

Page 17: ...me Stamp Counter Control 0x4A8 9 61 UARBCTC U Bus Arbiter Current Transfer Count 0x45C 9 60 UARBTC U Bus Arbiter Transfer Count 0x458 9 59 VCR0CAP VC Resource 0 Capability 0x210 9 45 VCR0CTL VC Resour...

Page 18: ...IDT Register List PES24N3A User Manual xii April 10 2008 Notes...

Page 19: ...rs consist of SerDes Physical Data Link and Transaction layers The PES24N3A can operate either as a store and forward switch or a cut through switch and is designed to switch memory and I O transactio...

Page 20: ...hieve low typical power consumption Supports PCI Power Management Interface specification PCI PM 1 1 Supports device power management states D0 D3hot and D3cold Unused SerDes are disabled Testability...

Page 21: ...Switch Core Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer Demultiplexer T...

Page 22: ...S RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE 3 0 4 2 2 CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE PE0RP 0 PE0RN 0 PE0RP 7 PE0RN 7 PCI Express Switch SerDes Input PE0TP...

Page 23: ...ID values the Next Pointer NXTPTR field in one of the other enhanced capabilities should be initialized to point to this capability Finally the Next Pointer NXTPTR of this capability should be adjust...

Page 24: ...press Port 4 Serial Data Transmit Differential PCI Express trans mit pairs for port 4 PEREFCLKP 2 1 PEREFCLKN 2 1 I PCI Express Reference Clock Differential reference clock pair input This clock is us...

Page 25: ...pin Alternate function pin name IOEXPINTN2 Alternate function pin type Input Alternate function I O Expander interrupt 2 input GPIO 5 I O General Purpose I O This pin can be configured as a general pu...

Page 26: ...em clock with a nominal 50 duty cycle JTAG_TDI I JTAG Data Input This is the serial data input to the boundary scan logic or JTAG Controller JTAG_TDO O JTAG Data Output This is the serial data shifted...

Page 27: ...VSS I Ground Function Pin Name Type Buffer I O Type Internal Resistor1 Notes PCI Express Interface PE0RN 7 0 I CML Serial link PE0RP 7 0 I PE0TN 7 0 O PE0TP 7 0 O PE2RN 7 0 I PE2RP 7 0 I PE2TN 7 0 O...

Page 28: ...I pull down EJTAG JTAG JTAG_TCK I LVTTL STI pull up JTAG_TDI I STI pull up JTAG_TDO O JTAG_TMS I STI pull up JTAG_TRST_N I STI pull up External pull down 1 Internal resistor values under typical oper...

Page 29: ...nd produces a 250 MHz core clock Clock Operation When the CCLKUS and CCLKDS pins are asserted they indicate that a common clock is being used between the upstream device and the upstream port as well...

Page 30: ...t disable Spread Spectrum Clock Figure 2 3 Common Clock on Upstream Non Common Clock on Downstream must disable Spread Spectrum Clock PES24N3A Port A Port B Port C CCLKDS CCLKUS REFCLK0 REFCLK1 EP EP...

Page 31: ...See Chapter 6 SMBus Interfaces for more information on the serial EEPROM The external serial EEPROM and slave SMBus interface may be used to override the function of some of the signals in the boot c...

Page 32: ...ntal reset may be initiated by any of the following conditions A cold reset initiated by a power on and the assertion of the PCI Express Reset PERSTN input pin A warm reset initiated by the assertion...

Page 33: ...zation from the serial EEPROM then the contents of the serial EEPROM are read and the appropriate PES24N3A registers are updated If an error is detected during loading of the serial EEPROM then loadin...

Page 34: ...ll of the logic associated with the PES24N3A except the PLLs SerDes master SMBus interface and slave SMBus interface is reset 3 All registers fields in all registers except those denoted as sticky or...

Page 35: ...am secondary bus reset may be initiated by the following condition A one is written to the Secondary Bus Reset SRESET bit in the upstream port s i e port 0 Bridge Control Register BRCTL When an upstre...

Page 36: ...stream port resets are tri stated A system designer should use a pull down on these signals if they are used as reset outputs The PES24N3A ensures through hardware that the minimum PxRSTN assertion pu...

Page 37: ...bserved The time between the assertion of the PxPWRGDN signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to Reset Negation PWR2RST field in the HPCFGCTL registe...

Page 38: ...IDT Clocking Reset and Initialization Clock Operation PES24N3A User Manual 2 10 April 10 2008 Notes...

Page 39: ...ream port D Bus and U Bus transfers may occur in parallel While not optimized for peer to peer traffic the PES24N3A supports these transfers A peer to peer transfer occurs by first transferring a TLP...

Page 40: ...cessed by a stack and queued in an output and replay buffer in continuous TLP manner Data is read from the output and replay buffer by the data link layer in a TDM manner The physical layer demultiple...

Page 41: ...us to the D Bus In addition to providing a data path between the U Bus and the D Bus the bus decoupler provides adequate buffering to accommodate one maximum sized TLP to allow the U Bus and D Bus to...

Page 42: ...eue non posted queue the completion transaction queue comple tion queue and an insertion buffer to hold TLPs generated by the stack While there are four physical queues in the IFB TLPs in the insertio...

Page 43: ...PES24N3A strongly order transactions regardless of the state of the relaxed ordering attribute Scheduling and Port Arbitration Associated with each port is an Egress Selection Picker ESP and associat...

Page 44: ...ers occur from the upstream port insertion buffer output through the U Bus multiplexor and to the upstream port The request for this transfer class comes from the candidate vector produced by the upst...

Page 45: ...o back 3 Dword TLPs the maximum overhead introduced by the D Bus arbiter is one clock cycle per TLP There are two D Bus transfer classes They are upstream to downstream and bus decoupler queue transfe...

Page 46: ...ration in this mode The PES24N3A also supports selective disabling of peer to peer transactions in a matrix fashion Asso ciated with each port is TLP Routing Control Px_TROUTECTL register Each bit in...

Page 47: ...ocked device and receiving a CplDLk or CplLk response from the locked device These transactions do not change the state of the switch when the switch is locked Therefore a CplLk completion once the sw...

Page 48: ...S24N3A supports legacy PCI INTx emulation Rather than use sideband INTx signals PCIe defines two messages that indicate the assertion and negation of an interrupt signal An Assert_INTx message is used...

Page 49: ...in the upstream port generating a Deassert_Intx message Standard PCIe Error Detection and Handling This section describes standard PCIe error detection and handling as prescribed by the PCIe base 1 1...

Page 50: ...5 2 1 Correctable error processing Violation of flow control initialization protocol 3 3 1 Uncorrectable error processing Sequence number specified by AckNak_Seq does not correspond to an unacknowledg...

Page 51: ...eceived by the switch i e by the stack associated with the port on which the switch receives the TLP Completer abort Completion time out 2 3 1 2 8 Not applicable The PES24N3A never generates non poste...

Page 52: ...lex rout ing May only be received on downstream ports TLPs with Broadcast from Root Com plex routing May only be received on upstream ports TLPs with Gathered and Routed to Root Complex routing May on...

Page 53: ...ort device number i e target a PCI to PCI bridge device number that doesn t exist Type 1 requests that route through the PES24N3A target a downstream port s link partner i e are converted to a Type 0...

Page 54: ...me out occurs then the switch core will abort processing of the TLP This may result in the broadcast TLP being transmitted on some but not all downstream pots End to End Parity Checking PCI Express pr...

Page 55: ...modified by the root serial EEPROM or slave SMBus master In addition to TLPs that flow through the switch cases exist in which TLPs are produced and consumed by the switch e g a configuration requests...

Page 56: ...il 10 2008 Notes requests that are Message Signaled Interrupts MSIs and Message requests except where specifically permitted Since MSIs cannot be distinguished from memory write transactions by the sw...

Page 57: ...corresponding port s PCI Express Link Status PCIELSTS register The Maximum Link Width MAXLNKWDTH field in a port s PCI Express Link Capabilities PCIELCAP register contains the maximum link width of t...

Page 58: ...ExRP 7 PES24N3A lane 0 lane 1 a x2 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES24N3A lane 1 lane 0 b x2 Port with lane reversal PExRP 0 PExRP 1 PExRP...

Page 59: ...PExRP 7 PES24N3A lane 3 lane 2 lane 1 lane 0 b x4 Port with lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES24N3A lane 0 lane 1 c x2 Port without lane reversal PExRP...

Page 60: ...PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES24N3A lane 0 lane 1 lane 2 lane 3 lane 4 lane 5 lane 6 lane 7 a x8 Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP...

Page 61: ...n to the Captured Slot Power Limit Scale CSPLS field Byte 1 bits 1 0 of the message payload are written to the Captured Slot Power Limit Value CSPLV field Downstream Port A Set_Slot_Power_Limit messag...

Page 62: ...transmit a TLP There are no DLLPs pending for transmission on the upstream port The downstream switch ports have the following L0s entry conditions The receive lanes of the switch upstream port are i...

Page 63: ...to provide a visual indication of system state and activity or for debug The PxLINKUP output is asserted when the PCI Express data link layer is up i e when the LTSSM is in the L0 L0s L1 or recovery s...

Page 64: ...IDT Link Operation PES24N3A User Manual 4 8 April 10 2008 Notes...

Page 65: ...ated as asynchronous inputs When a GPIO pin is configured to use the GPIO function the unneeded alternate function associated with the pin is held in an inactive state by internal logic Note Care shou...

Page 66: ...r alternate function GPIO Pin Configured as an Output When configured as an output in the GPIOCFG register and as a GPIO function in the GPIOFUNC register the value in the corresponding bit position o...

Page 67: ...split configuration Figure 6 1 SMBus Interface Configuration Examples In the unified configuration shown in Figure 6 1 a the master and slave SMBuses are tied together and the PES24N3A acts both as a...

Page 68: ...Table 6 1 Device Initialization from a Serial EEPROM During initialization from the optional serial EEPROM the master SMBus interface reads configuration blocks from the serial EEPROM and updates cor...

Page 69: ...PE field that indicates the type of the configuration block For single double word initialization sequence this value is always 0x0 The final DATA field contains the double word initialization value F...

Page 70: ...uration Done Sequence Format The checksum in the configuration done sequence enables the integrity of the serial EEPROM initializa tion to be verified Since uninitialized EEPROMs typically have a valu...

Page 71: ...of the serial EEPROM location to be read and the Operation OP field to read The Busy BUSY bit should then be checked If the EEPROM is not busy the read operation may be initiated by performing a write...

Page 72: ...iated with LED control i e link status and activity are active low i e driven low when an LED should be turned on I O expander signals associated with hot plug signals are not inverted During the PES2...

Page 73: ...O 0 0 through I O 0 7 to I O expander register 6 Write the configuration value to select all inputs upper eight I O expander bits i e I O 1 0 through I O 1 7 to I O expander register 7 Read value of...

Page 74: ...bounce circuitry The I O expander interrupt request output is negated whenever the input values are read or when the input pin changes state back to the value previously read The PES24N3A ensures that...

Page 75: ...modifications that correspond to hot plug outputs result in SMBus transac tions This includes modifications due to upstream secondary bus resets and hot resets 5 I O expander outputs are not modified...

Page 76: ...P2PWRGDN Port 2 power good input 11 I O 1 3 I Reserved Tie high 12 I O 1 4 I P4PWRGDN Port 4 power good input 13 I O 1 5 I Reserved Tie high or low 14 I O 1 6 I Reserved Tie high or low 15 I O 1 7 I R...

Page 77: ...ailed description of these transactions Byte and Word Write Read Block Write Read Initiation of any SMBus transaction other than those listed above to the slave SMBus interface produces undefined resu...

Page 78: ...and END signifies a single transaction sequence 0 Current transaction is not the last read or write sequence 1 Current transaction is the last read or write sequence 1 START Start of transaction indi...

Page 79: ...the doubleword CSR system address of register to access 4 ADDRU Address Upper Upper 6 bits of the doubleword CSR sys tem address of register to access Bits 6 and 7 in the byte must be zero and are ig...

Page 80: ...ption 0 CCODE Command Code Slave Command Code field described in Table 6 9 1 BYTCNT Byte Count The byte count field is only transmitted for block type SMBus transactions SMBus word and byte accesses t...

Page 81: ...ster 2 Reserved 3 NAERR RC No Acknowledge Error This bit is set if an unexpected NACK is observed during a master SMBus transaction when accessing the serial EEPROM This bit has the same function as t...

Page 82: ...S PES24N3A Slave SMBus Address Wr A N CCODE START END P PES24N3A not ready with data S PES24N3A Slave SMBus Address Wr A A BYTCNT 4 A CMD read A EEADDR A ADDRL A P CCODE START END S PES24N3A Slave SM...

Page 83: ...s with PEC Disabled Figure 6 12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled S PES24N3A Slave SMBus Address Wr A A BYTCNT 5 A CMD write A EEADDR A ADDRL A CCODE START END...

Page 84: ...RT Word S PES24N3A Slave SMBus Address Rd DATALM DATALL A N P P S PES24N3A Slave SMBus Address Wr A A ADDRU A CCODE END Byte P A S PES24N3A Slave SMBus Address Wr A CCODE Byte A P A S PES24N3A Slave S...

Page 85: ...e entire device When the upstream port enters a low power state and the PME_TO_Ack messages are received then the entire device is placed into a low power state The PES24N3A supports the following dev...

Page 86: ...is includes both the case when the downstream port is in the D3hot state or the entire switch is in the D3hot state The generation of a PME message by downstream ports necessitates the implementation...

Page 87: ...nstream port that does not receive a PME_TO_Ack message in the time out period specified in the PME_TO_Ack Time Out PMETOATO field in its corresponding PME_TO_Ack Timer PMETOATIMER register declares a...

Page 88: ...IDT Power Management PES24N3A User Manual 7 4 April 10 2008 Notes...

Page 89: ...upstream port serves as the add in card s PCIe interface In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 8 3 illustrates the use of the PES24N3A...

Page 90: ...t is implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug messa...

Page 91: ...MICTL bit in the HPCFGCTL register is set writing a one to the EIC bit inverts the state of the PxILOCKP signal When the Replace MRL Status with EMIL Status RMRLWEMIL bit is set in the HPCFGCTL regist...

Page 92: ...the downstream port or the entire switch is in a D3Hot state the hot plug controller generates a wake up event using a PM_PME message instead of an interrupt if the event inter rupt is not masked in...

Page 93: ...form of a pseudo logic diagram Logic gates in this diagram are intended for conveying general concepts and not for direct implementation Note Logic gates in this diagram are intended to convey genera...

Page 94: ...ltage Since no clock is present during physical connection the device will maintain all outputs in a high impedance state even when no clock is present The I O cells meet VI requirements for hot swap...

Page 95: ...As shown in Figure 9 1 upstream and downstream ports share a similar PCI configuration space register layout The upstream port contains global switch control and status registers as well as test mode...

Page 96: ...ort Only Power Budgeting Enhanced Capability PCIe Virtual Channel Enhanced Capability Device Serial Number Enhanced Capability Advanced Error Reporting Enhanced Capability 0x000 0x040 0x0D0 0x0F8 Type...

Page 97: ...rd P0_BAR1 BAR1 Base Address Register 1 0x014 on page 9 15 0x018 Byte P0_PBUSN PBUSN Primary Bus Number Register 0x018 on page 9 15 0x019 Byte P0_SBUSN SBUSN Secondary Bus Number Register 0x019 on pag...

Page 98: ...0_PCIEDSTS2 PCIEDSTS2 PCI Express Device Status 2 0x06A on page 9 31 0x06C DWord P0_PCIELCAP2 PCIELCAP2 PCI Express Link Capabilities 2 0x06C on page 9 31 0x070 Word P0_PCIELCTL2 PCIELCTL2 PCI Express...

Page 99: ...esource 0 Capability 0x210 on page 9 45 0x214 DWord P0_VCR0CTL VCR0CTL VC Resource 0 Control 0x214 on page 9 46 0x218 DWord P0_VCR0STS VCR0STS VC Resource 0 Status 0x218 on page 9 46 0x220 DWord P0_VC...

Page 100: ...s 0x424 on page 9 54 0x428 DWord SMBUSCTL SMBUSCTL SMBus Control 0x428 on page 9 55 0x42C DWord EEPROMINTF EEPROMINTF Serial EEPROM Interface 0x42C on page 9 56 0x430 DWord IOEXPINTF IOEXPINTF I O Exp...

Page 101: ...Time Out Control 0x750 on page 9 62 0x754 Dword P0_SWTOSTS SWTOSTS Switch Time Out Status 0x754 on page 9 62 0x758 Dword P0_SWTORCTL SWTORCTL Switch Time Out Reporting Control 0x758 on page 9 63 0x75C...

Page 102: ...rd Px_BAR1 BAR1 Base Address Register 1 0x014 on page 9 15 0x018 Byte Px_PBUSN PBUSN Primary Bus Number Register 0x018 on page 9 15 0x019 Byte Px_SBUSN SBUSN Secondary Bus Number Register 0x019 on pag...

Page 103: ...PCIEDCAP2 PCI Express Device Capabilities 2 0x064 on page 9 31 0x068 Word Px_PCIEDCTL2 PCIEDCTL2 PCI Express Device Control 2 0x068 on page 9 31 0x06A Word Px_PCIEDSTS2 PCIEDSTS2 PCI Express Device St...

Page 104: ...d Doubleword 0x120 on page 9 42 0x124 Dword Px_AERHL3DW AERHL3DW AER Header Log 3rd Doubleword 0x124 on page 9 42 0x128 Dword Px_AERHL4DW AERHL4DW AER Header Log 4th Doubleword 0x128 on page 9 43 0x18...

Page 105: ...Budgeting Data Value 0 7 0x300 on page 9 50 0x31C Dword Px_PWRBDV7 PWRBDV 0 7 Power Budgeting Data Value 0 7 0x300 on page 9 50 0x740 Dword Px_SWPECTL SWPECTL Switch Parity Error Control 0x740 on page...

Page 106: ...er direction or the forwarding of non memory or I O requests 0x0 disable Disable request forwarding 0x1 enable Enable request forwarding 3 SSE RO 0x0 Special Cycle Enable Not applicable 4 MWI RO 0x0 M...

Page 107: ...te that the bridge implements an extended capability list item 5 C66MHZ RO 0x0 66 MHz Capable Not applicable 6 Reserved RO 0x0 Reserved field 7 FB2B RO 0x0 Fast Back to Back FB2B Not applicable 8 MDPE...

Page 108: ...btractive decode 15 8 SUB RO 0x04 Sub Class Code This value indicates that the device is a PCI PCI bridge 23 16 BASE RO 0x06 Base Class Code This value indicates that the device is a bridge Bit Field...

Page 109: ...ield is used to record the bus number of the PCI bus segment to which the primary inter face of the bridge is connected This field has no functional effect within the PES24N3A but is implemented as a...

Page 110: ...IOBASE and IOLIMIT registers are used to control the forwarding of I O transactions between the pri mary and secondary interfaces of the bridge This field con tains A 15 12 of the highest I O address...

Page 111: ...IT RW 0x0 Memory Address Limit The MBASE and MLIMIT registers are used to control the forwarding of non prefetchable trans actions between the primary and secondary interfaces of the bridge This field...

Page 112: ...ld contains A 31 20 of the highest memory address with A 19 0 assumed to be 0xF_FFFF that is below the primary interface of the bridge PMLIMITU specifies the remaining bits Bit Field Field Name Type D...

Page 113: ...Expansion ROM Base Address The bridge does not implement an expansion ROM Thus this field is hardwired to zero Bit Field Field Name Type Default Value Description 7 0 INTRLINE RW 0x0 Interrupt Line T...

Page 114: ...ard downstream all I O addresses in the address range defined by the I O base and I O limit reg isters 1 enable Forward upstream ISA I O addresses in the address range defined by the I O base and I O...

Page 115: ...RWL 0x1 TCS Routing Supported The PES24N3A supports TCS routing The default value of this field is 0x0 in PCIe 1 1 mode 31 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Descr...

Page 116: ...it in Watts calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field The value of this field is set by a Set_Slot_Power_Limit Message and is only applicable f...

Page 117: ...ransactions through the bridge with the No Snoop bit unmodified 14 12 MRRS RO 0x0 Maximum Read Request Size The bridge does not gener ate transactions larger than 128 bytes and passes transac tions th...

Page 118: ...16 x16 link width 32 x32 x32 link width others reserved 11 10 ASPMS RO 0x3 Active State Power Management ASPM Support This field is hardwired to 0x3 to indicate L0s and L1 Support 14 12 L0SEL RWL see...

Page 119: ...x0 Port 2 0x2 Port 4 0x4 Port Number This field indicates the PCI express port num ber for the corresponding link Bit Field Field Name Type Default Value Description 1 0 ASPM RW 0x0 Active State Power...

Page 120: ...RMGT RO 0x0 Enable Clock Power Management The PES24N3A does not support this feature 9 HWAWDTH DIS RW 0x0 Hardware Autonomous Width Disable When set this bit disables hardware from changing the link w...

Page 121: ...state A link retraining initiated by setting the LRET bit in the PCIELCTL register has completed The PHY has autonomously changed link speed or width to attempt to correct unreliable link operation ei...

Page 122: ...d by the slot A Set_Slot_Power_Limit message is generated using this field whenever this register is written or when the link transi tions from a non DL_Up status to a DL_Up status This bit is read on...

Page 123: ...bled in the PCIESCAP regis ter 3 PDCE RW 0x0 Presence Detected Changed Enable This bit when set enables the generation of a Hot Plug interrupt or wake up event on a presence detect change event 4 CCIE...

Page 124: ...ro when read If an electromechanical interlock is implemented a write of a one to this field causes the state of the interlock to toggle and a write of a zero has no effect This bit is read only and h...

Page 125: ...ent status of the interlock 0x0 disengaged Electromechanical interlock disengaged 0x1 engaged Electromechanical interlock engaged 8 DLLLASC RW1C 0x0 Data Link Layer Link Active State Change This bit i...

Page 126: ...unsupported value produces undefined results 1 gen1 2 5 Gbps 2 gen2 5 Gbps others reserved This field is read only zero in PCIe 1 1 mode 4 ECOMP RW 0x0 Sticky Enter Compliance Software is permitted t...

Page 127: ...18 16 VER RO 0x3 Power Management Capability Version This field indi cates compliance with version two of the specification Complies with version the PCI Bus Power Management Interface Specification...

Page 128: ...ed when exiting the D3cold state then this bit should be set during serial EEPROM ini tialization A hot reset does not result in modification of this field 12 9 DSEL RO 0x0 Data Select The optional da...

Page 129: ...targeted to the root and routes these trans actions to the upstream port Configuring the address contained in a downstream port s MSIADDR and MSIAD DRU registers to an address that does not route to t...

Page 130: ...tructure 15 8 NXTPTR RWL 0x00 Next Pointer This field contains a pointer to the next capa bility structure 31 16 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 15 0...

Page 131: ...f this field return a value of zero and SMBus writes have no effect Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x1 Capability ID The value of 0x1 indicates an advanced error rep...

Page 132: ...ked When a bit is masked in the AERUES register the corresponding event is not logged in the advanced capability structure and an error is not reported to the root complex 5 SDOENERR RW 0x0 Sticky Sur...

Page 133: ...orresponding event is not logged in the advanced capability structure and an error is not reported to the root complex 20 UR RW 0x0 Sticky UR Mask When this bit is set the corresponding bit in the AER...

Page 134: ...d as a fatal error When this bit is cleared the event is reported as an uncor rectable error 17 RCVOVR RW 0x1 Sticky Receiver Overflow Severity If the corresponding event is not masked in the AERUEM r...

Page 135: ...ication 31 14 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 0 RCVERR RW 0x0 Sticky Receiver Error Mask When this bit is set the correspond ing bit in the AERCES re...

Page 136: ...e is capable of generating ECRC 6 ECRCGE RW 0x0 Sticky ECRC Generation Enable When this bit is set ECRC gen eration is enabled 7 ECRCCC RWL 0x1 ECRC Check Capable This bit indicates if the device is c...

Page 137: ...ity Version The value of 0x1 indicates compatibil ity with version 1 of the specification 31 20 NXTPTR RWL 0x200 Next Pointer Bit Field Field Name Type Default Value Description 31 0 SNUM RWL 0x0 Stic...

Page 138: ...bit2 Port arbitration table is 2 bits 0x2 bit4 Port arbitration table is 4 bits 0x3 bit8 Port arbitration table is 8 bits 31 12 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value D...

Page 139: ...VC arbitration table Since the device sup ports only VC0 this field has no functional effect and is always zero 31 1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description...

Page 140: ...ort Arbitra tion Capability field selected by Port Arbitration Select Software sets this bit to signal hardware to update Port Arbi tration logic with new values stored in Port Arbitration Table clear...

Page 141: ...an invalid port ID results in the entry being skipped without delay The port arbitration behavior when this field contains an ille gal value i e reserved or the egress port ID is undefined 0x0 port_0...

Page 142: ...od 7 4 PHASE17 RW 0x0 Phase 17 This field contains the port ID for the correspond ing port arbitration period 11 8 PHASE18 RW 0x0 Phase 18 This field contains the port ID for the correspond ing port a...

Page 143: ...alized with data from a serial EEPROM 19 16 CAPVER RWL 0x0 Capability Version The value of 0x1 indicates compatibil ity with version 1 of the specification If the power budgeting capability is used th...

Page 144: ...tch Control SWCTL register When the PWRBDVUL bit is cleared this register is read only and writes are ignored If the power budgeting capability is used then this field should be initialized with data...

Page 145: ...value of zero when read See section Fundamental Reset on page 2 4 for the behav ior of this bit 1 HRST RW 0x0 Hot Reset Writing a one to this bit initiates a hot reset Writ ing a zero has no effect Th...

Page 146: ...ansactions received on a downstream port which are not destined to the upstream port are treated as an unsupported requests 13 9 Reserved RO 0x0 Reserved field 14 CTDIS RW 0x0 Sticky Disable Cut Throu...

Page 147: ...ts are used as electromechani cal lock state inputs 13 TEMICTL RW 0x0 Sticky Toggle Electromechanical Interlock Control When this bit is cleared the Electromechanical Interlock PxILOCKP output is puls...

Page 148: ...utput When a bit is configured as a general purpose I O pin and the corre sponding bit in this field is zero then the pin is configured as an input When the pin is configured as an alternate func tion...

Page 149: ...0x0 Initialization Checksum Error This bit is set if an invalid checksum is computed during Serial EEPROM initialization or when a configuration done command is not found in the serial EEPROM 29 URIA...

Page 150: ...interface fast mode Glitch counters operate with 100nS delay 0x2 disabled Master SMBus interface with glitch counters disabled Glitch counters operate with zero delay which effectively removes them 0...

Page 151: ...de IOEXTM bit is set When the IOEXTM bit is set the value for outputs supplied to the I O expander selected by the SEL field correspond to the value written to this field instead of the value supplied...

Page 152: ...e I O expander initial ization sequence completes Bit Field Field Name Type Default Value Description 0 Reserved RO 0x0 Reserved field 7 1 IOE0ADDR RWL 0x0 Sticky I O Expander 0 Address This field con...

Page 153: ...ort is signalling a general purpose event by asserting the GPEN signal This bit is never set if the cor responding general purpose event is not enabled in the GPECTL register GPEN is an alternate func...

Page 154: ...r Count This field con tains the current upstream to self transfer count 31 24 D2SCTC RO 0x01 Downstream to Downstream Current Transfer Count This field contains the current downstream to self transfe...

Page 155: ...not be dis abled 1 GBEEP RW 0x0 Sticky Generate Bad End to End Parity When this bit is set bad parity is generated for all double words in TLPs emitted to the switch core from this port i e those rece...

Page 156: ...ld Name Type Default Value Description 7 0 EEPEC RCW 0x0 Sticky End to End Parity Error Count This field is incremented each time an end to end parity error is detected at the port until it saturates...

Page 157: ...port generates an ERR_FATAL message to the root 3 2 NPTLPTO RW 0x0 Sticky Non Posted TLP Time Out Reporting This field controls the manner in which non posted TLP time outs are reported A time out is...

Page 158: ...s it to be cleared 15 8 NPTLPTOC RCW 0x0 Sticky Non Posted TLP Time Out Count This field is incre mented each time a TLP is discarded from the port s IFB non posted queue because it is more than 50 ms...

Page 159: ...er is greater than or equal to this value then time stamp epoch values contained in bits 33 and 34 of the time stamp are incremented The default value of 0x1DD corresponds to an epoch interval of 32 S...

Page 160: ...IDT Configuration Registers PES24N3A User Manual 9 66 April 10 2008 Notes...

Page 161: ...Test Access Point The system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Controll...

Page 162: ...active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the fallin...

Page 163: ...E2RP 7 0 I O PE2TN 7 0 O C PE2TP 7 0 PE4RN 7 0 I O PE4RP 7 0 I O PE4TN 7 0 O C PE4TP 7 0 PEREFCLKN 2 1 I PEREFCLKP 2 1 I REFCLKM I O SMBus MSMBADDR 4 1 I O MSMBCLK I O O C MSMBDAT I O O C SSMBADDR 5 3...

Page 164: ...sses through the UPDATE IR state whatever value that is currently held in the boundary scan register s output latches is immediately transferred to the corresponding outputs or output enables Therefor...

Page 165: ...Output Enable Cell is driving a high out to the pad which enables the pad for output and EXTEST is disabled the Capture Cell will be configured to capture output data from the core to the pad However...

Page 166: ...troller passes through the UPDATE DR state these values will be latched onto the output pins or into the output enables Instruction Definition Opcode EXTEST Mandatory instruction allowing the testing...

Page 167: ...is register to devices further down stream IDCODE The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by the use of the JTAG_TRST_N signal or by the ap...

Page 168: ...ructions Usage Considerations As previously stated there are internal pull ups on JTAG_TRST_N JTAG_TMS and JTAG_TDI However JTAG_TCK also needs to be driven to a known value It is best to either drive...

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