IDT 89HPES24N3A, User Manual

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IDT Theory of Operation
PES24N3A User Manual 3 - 5 April 10, 2008
Notes
The generation of “valid” signals is based on PCIe ordering rules and is summarized Table 3.6. The
notation x > y indicates that the TLP of type x is older (i.e., has an older time-stamp) than the TLP of type y.
It is impossible for two TLPs to have the same timestamp. The notation x.ro indicates that the relaxed
ordering attribute is set in the header of the TLP at the head of logical queue type x. Table 3.6 only lists the
relaxed ordering attributes in cases where it affects the state of a valid signal.
When two logical TLP types are destined to the same egress port from the same ingress port, the rela-
tive TLP type age is used to order the TLPs (i.e., the older one is allowed to progress first). Other than the
ordering rules shown in Table 3.6, relative age plays no role in ordering of TLPs destined to different egress
ports from the same ingress ports. Thus, TLPs destined to different egress ports may be aggressively reor-
dered even when there is no congestion in the system.
Since ordering is performed by examining the heads of the three logical IFB queues, TLPs of a particular
type are never reordered (i.e., a posted will never bypass another posted with an earlier timestamp).
When the Disable Relaxed Ordering (DRO) bit is set in the Switch Control (SWCTL) register, all of the
IFBs in the PES24N3A strongly order transactions regardless of the state of the relaxed ordering attribute.
Scheduling and Port Arbitration
Associated with each port is an Egress Selection Picker (ESP) and associated with each bus (i.e., U-
Bus or D-Bus) is a bus arbiter. The function of the ESP is to provide a candidate vector with one bit per port
indicating which ports have a TLP in their input frame buffer or insertion buffer that can be transferred to
that output port.
In producing the candidate vector, each port’s ESP takes the following factors into consideration.
– The availability and ordering, as reported by each port’s Input Frame Buffer (IFB), of TLPs of each
type (i.e., posted, non-posted, completion, and insertion) that can be transferred from the head of
the port’s IFB queues.
– The size of each TLP type that can be transferred from each port’s IFB queues.
– The amount of space available in the corresponding (i.e., the port with which the ESP is associ-
ated) port’s output and replay buffer.
– The ability of the application layer in the corresponding port to accept a TLP not destined to that
port’s egress (e.g., one that is processed by the completion processor).
– The number of PCIe header and data credits available of each TLP type indicated by the corre-
sponding port’s link partner.
– The occupancy of the bus decoupler queue.
Logical Queue Head
Ordering
Posted Valid
Non-Posted
Valid
Completion
Valid
P > NP > CP.ro 1 0 1
P > NP > CP 1 0 0
P > CP > NP 1 0 0
P > CP.ro > NP 1 1 0
NP > P > CP 1 1 0
NP > P > CP.ro 1 1 1
NP > CP > P 1 1 1
CP > P > NP 1 0 0
CP > NP > P 1 1 1
Table 3.6 IFB Transaction Ordering