IDT 89HPES24N3A, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES24N3A User Manual 2 - 5 April 10, 2008
Notes
The following reset sequence is executed.
1. Wait for the fundamental reset condition to clear (e.g., negation of PERSTN).
2. On negation of PERSTN, sample the boot configuration signals listed in Table 2.2. If PERSTN was
not asserted, use the previously sampled boot configuration signal values (e.g., when a fundamental
reset is the result of a one being written to the FRST bit in the SWCTL register). Examine the state
of the sampled SWMODE[3:0] signals to determine the switch operating mode.
3. Initialize the PLL and SerDes.
4. Begin link training. While link training is in progress, proceed to step 5.
5. If the Reset Halt (RSTHALT) pin is asserted, set the RSTHALT bit in the SWSTS register.
6. If the switch operating mode is not a test mode, then the reset signal to the PCI Express phy, data
link, and transaction layers (stacks) and associated logic is negated, but these stacks are held in a
quasi-reset state in which the following actions occur:
– All links enter an active link training state within 20ms of the clearing of the fundamental reset
condition.
– Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration request
retry status completion. All other transactions are ignored.
7. The master SMBus operating frequency is determined.
The state of the MSMBSMODE signal is examined. If it is asserted, then the master SMBus is ini-
tialized to operate at 100 KHz rather than 400 KHz.
8. The slave SMBus is taken out of reset and initialized. The slave SMBus address specified by the
SSMBADDR[5,3:1] pins is used.
9. The master SMBus is taken out of reset and initialized.
10. If the selected switch operating mode is one that requires initialization from the serial EEPROM, then
the contents of the serial EEPROM are read and the appropriate PES24N3A registers are updated.
– If an error is detected during loading of the serial EEPROM, then loading of the serial EEPROM
is aborted and the RSTHALT bit is set in the SWCTL register. Error information is recorded in the
SMBUSSTS register.
– When serial EEPROM initialization completes or when an error is detected, the DONE bit in the
SMBUSSTS register is set.
11. If the Reset Halt (RSTHALT) bit is set in the SWCTL register, all of the logic is held in a reset state
except the master and slave SMBuses, the control/status registers, and the stacks which continue
to be held in a quasi-reset state and respond to configuration transactions with a retry. The device
remains in this state until the RSTHALT bit is cleared via the slave SMBus. In this mode, an external
agent may read and write any internal control and status registers and may access the external
serial EEPROM via the EEPROMINTF register.
12. Normal device operation begins.
The PCIe base specification indicates that normal operation should begin within 1.0 second after a
fundamental reset of a device. The reset sequence above guarantees that normal operation will begin
within this period as long as the serial EEPROM initialization process completes within 200 ms. Under
normal circumstances, 200 ms is more than adequate to initialize registers in the device even with a Master
SMBus operating frequency of 100 KHz.
Serial EEPROM initialization may cause writes to register fields that initiate side effects such as link
retraining. These side effects are initiated at the point at which the write occurs. Therefore, serial EEPROM
initialization should be structured in a manner so as to ensure proper configuration prior to initiation of these
side effects.
A warm reset initiated by the writing of a one to the Fundamental Reset (FRST) bit in the Switch Control
(SWCTL) register always results in the PES24N3A returning a completion to the requester before the warm
reset process begins.